DRAM

Why is the voltage change on the bit line very small when DRAM is read?

  1. ABecause the supply voltage is very high
  2. BBecause the bit line resistance is zero
  3. CBecause the cell capacitor's capacitance is much smaller than the bit line's parasitic capacitance
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Answer: C. Because the cell capacitor's capacitance is much smaller than the bit line's parasitic capacitance

During a read, the cell capacitor's charge is shared with the bit line. The cell capacitance is much smaller than the bit line capacitance, so the bit line voltage changes only slightly (tens to around a hundred-odd mV). The sense amplifier amplifies this small change to decide 0 or 1.

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More DRAM questions

  1. Which correctly describes the idea of 3D DRAM, under research and development as a way to increase future DRAM capacity?
  2. In DRAM, what is the phenomenon in which repeatedly activating one row in a short time can flip data in adjacent rows?
  3. Which correctly describes the main leakage paths that determine the data retention time of DRAM cells?
  4. What does F mean in '6F²', used to express DRAM cell area?
  5. In DRAM access, what is the operation called that closes the open row and returns the bit lines to an intermediate voltage to prepare for activating the next row?