DRAM

Which correctly describes the idea of "8n prefetch" used in memories such as DDR4 SDRAM?

  1. AData eight times the I/O width is fetched from the internal array at once and output in sequence at high speed through the external pins
  2. BEight refresh operations are performed together
  3. CThe same data is written to eight chips
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Answer: A. Data eight times the I/O width is fetched from the internal array at once and output in sequence at high speed through the external pins

Because the DRAM cell array itself cannot run much faster, the device internally reads eight times the I/O width (8n) in a single access and sends it out in sequence over the fast external interface. This raises the external transfer rate without speeding up the internal array.

  • A. Correct. Wide data is read internally and output quickly externally.
  • B. It is not a mechanism for grouping refreshes.
  • C. It is not a mechanism for writing the same data to several chips.
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More DRAM questions

  1. In DDR-family DRAM, which feature places termination resistors inside the DRAM chip, with controllable on/off, to suppress signal reflections?
  2. Some DRAM cells have a data retention time that irregularly switches between longer and shorter values over time. What is this phenomenon called?
  3. Why is a boosted voltage (VPP), higher than the supply voltage, used to drive DRAM word lines?
  4. Which correctly describes the structure of a typical 1-bit DRAM memory cell?
  5. Why does DRAM need periodic refresh operations?