Logic circuits

What is the state called when a flip-flop receiving an asynchronous signal violates setup or hold time and its output is temporarily neither 0 nor 1?

  1. AMetastability
  2. BGlitch
  3. CLatch-up
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Answer: A. Metastability

In a metastable state, the output may linger at an intermediate voltage or take a long time to settle. To prevent problems, asynchronous signals are received by a synchronizer of two or more flip-flops in series, making the probability that an undefined value propagates to later stages sufficiently small.

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