How Are Chips Tested? Wafer Test, Final Test and Burn-In

In everyday life

Every chip in your phone or computer passed tests several times before it shipped. A smartphone processor holds billions of tiny switches. You cannot tell good from bad just by looking at it. So machines feed in electrical signals and check that the right answers come back.

If you join a chip company, you will often hear words like "test," "yield" and "bin." Factory staff use them, and so do sales and purchasing staff when they talk about prices and delivery dates. This article explains these words in the order of the process.

The big picture: inspection and electrical testing

The work of finding defects falls into two broad kinds. The first looks at wafers partway through manufacturing. Optical or electron microscopes search for particles and shape errors, and measure dimensions. The second runs electricity through the finished chips to check that they work correctly.

In this article, we call the first kind "inspection" and the second "testing." In practice, people often use one word for both, so this is not a strict rule. The stage that builds circuits on the wafer is called the front end. The stage that cuts the wafer into chips and packages them is called the back end. The figure below shows where chips are checked as they move through the process.

Why testing matters so much

However carefully chips are made, a certain share of the chips on each wafer will be faulty. The share of good chips among all the chips made is called the yield. When yield is low, there are fewer chips to sell, and the cost of each chip goes up.

The later a defect is found, the more it costs. If a faulty chip is packaged, the packaging materials and work are wasted. If it has already been soldered onto the circuit board inside a device, the whole board must be repaired or thrown away. If the product has already reached a customer, there are recall and replacement costs, and the company's reputation suffers.

That is why inspection and testing are placed at many points in the process, to stop defects as early as possible. But every check also costs time and equipment. Deciding where to check, what to check and how thoroughly is an important job in itself.

In-line inspection: looking and measuring

In the front end, films are added, patterns are printed and material is etched away, dozens of times over. Along the way, wafers go into special machines that check their condition. The aim is to confirm that each step came out as planned, and to fix the process early if something drifts.

The first kind of check searches for particles and for missing parts of patterns. When light shines on a wafer, it scatters wherever a particle sits. Another method compares images of neighboring chips and looks for differences. Machines like these are called defect inspection systems.

Not every defect found makes a chip fail. What makes a chip faulty is a defect that cuts a wire partway, or joins two wires that should be separate. Such a defect is called a killer defect. Reducing their number is the quickest way to raise yield.

The second kind of check measures dimensions at chosen spots. The width of the printed lines is measured with a special microscope that looks down from above with a fine beam of electrons. This microscope is called a CD-SEM.

Film thickness is worked out by shining light on the film and seeing how the reflected light has changed. One such method is called ellipsometry. It measures without touching the film, so production wafers can be checked as they are. Major makers of inspection and measurement machines include KLA in the US.

Wafer test: probing each chip with needles

When the front end is finished, the chips sit on the wafer in a neat grid. While they are still in this state, before being cut apart, each chip is tested electrically. This is called wafer test, also known as wafer probe or wafer sort.

The surface of each chip has a row of tiny metal pads that connect it to the outside. A part holding many fine needles is pressed onto those pads. This part is called a probe card. Its needles are arranged to match the positions of the chip's pads.

The machine that moves the wafer and lines up the needles exactly with the pads is called a prober. The main makers are Tokyo Electron and Tokyo Seimitsu. After each test, the prober moves the wafer so the needles reach the next chip. Sometimes several chips are tested at once.

Another machine creates signals and sends them in. It compares the answers with the correct ones and decides automatically whether the chip is good. This machine is the tester, formally called automatic test equipment (ATE). The main makers are Advantest of Japan and Teradyne of the US. For an overview of all the machines, see "Semiconductor Manufacturing Equipment."

The results are recorded for each chip position. This record is called a wafer map, and chips judged faulty are not packaged later. If faulty chips cluster in one area, that is a clue that something went wrong somewhere in the front end.

Final test: once more after packaging

The good chips are cut apart and packaged, which turns them into parts ("What Is Semiconductor Packaging?"). During packaging, a connecting wire may come loose or a chip may crack. So the finished part is tested again. This is called the final test.

In final test, a machine that carries the parts places each one into a test socket. This machine is called a handler. The handler heats or cools the parts so they can be measured at a set temperature. When the test is done, it sorts the parts into separate containers based on the results.

Chips are measured at different temperatures because their performance changes with temperature. For example, the car-parts standard AEC-Q100 defines temperature grades. The toughest, Grade 0, covers an ambient temperature of −40 to 150 °C. "Wafer Test vs Final Test" sets the two tests side by side in a table.

Burn-in: catching early failures before shipping

Chips tend to fail soon after they are first used. Small weak spots created during manufacturing show up early. After that comes a long period with few failures, and failures rise again as the chips near the end of their life. Because this shape looks like the cross-section of a bathtub, it is called the bathtub curve.

So, before shipping, chips can be run at a high temperature and a raised voltage, so that the weak ones fail first. This is called burn-in. The conditions differ by product. A commonly cited example is 125 °C for 168 hours (one week), from sources such as the US FDA's guide to inspecting electronic components.

Burn-in needs dedicated equipment and time. So it is not done on every product. It is used most for chips where a failure would be costly, such as chips for cars, industrial equipment and data-center servers. "Arrhenius Equation in Chips" explains why heat speeds up wear. "Static vs Dynamic vs Wafer-Level Burn-In" covers the different methods.

What electrical tests check

What a test checks differs by product. Here are typical items shared by many chips, roughly in the order they are run. Real test programs split them into many more items.

• Connection: First, check that the needles or pins are properly touching the chip's pads. If this fails, none of the other results can be trusted.
• Current that leaks: Measure the tiny current that flows even when a switch is off. Too much of it drains a battery faster. It is also a clue to defects where parts that should be separate are joined. This current is called leakage current.
• Function: Feed in a set pattern of 0s and 1s, and check that the answers match the correct ones.
• Speed: Run the chip's timing signal (the clock) at the target speed, and check that it still gives no wrong answers.
• Power: Measure the current drawn from the power supply while the chip is running and while it is idle. Looking for defects using the idle current is called IDDQ testing.

Sorting by speed: one design, several models

Even chips of the same design, made in the same factory, come out slightly different. Line widths and film thicknesses vary by tiny amounts. As a result, the top speed at which each chip can run without errors also differs a little.

So tests sometimes measure speed and split the chips into groups by the result. This sorting is called binning, and each group is called a bin, meaning a container. The fast group is sold as a higher model at a higher price, and the slow group as a lower model at a lower price. A 2007 university research paper also describes this as a common way to deal with variation.

But not every chip sold under a different model number has the same design. Makers often do not say which models are sorted from the same design. All we can say is this: chips of the same design may be sold differently depending on their test results.

Designing for testability: scan chains and BIST

A chip with billions of switches is very hard to test fully through its outside pins alone. The state of the circuits inside cannot be seen directly from outside. So mechanisms for testing are built into the chip from the design stage. This approach is called design for testability (DFT).

A chip contains many small circuits that each remember a single 0 or 1. These are called flip-flops. In normal use, they hold partial results of a calculation until the next clock tick.

Only during testing, these flip-flops are linked into a single line, like a chain. Shifting 0s and 1s in from the input lets you set the inner circuits to any values you want. The circuit is run just once, and the results are shifted out at the output and compared with the correct answers. This chain is called a scan chain, and testing with it is called scan testing.

The other method builds the testing circuit itself into the chip. The chip creates its own test values, checks whether the answers are correct, and reports only the result to the outside. This is called built-in self-test (BIST). It is often used for checking the memory inside a chip. "Scan Test vs BIST" compares the two.

Calculating yield with hypothetical numbers

Let's calculate yield with some made-up numbers. They are not figures from a real product, just an example to show the idea. Say one wafer holds 500 chips, and 450 of them pass wafer test. The wafer test yield is 450 ÷ 500, or 90%.

Next, the 450 passing chips are packaged and go through final test, and 441 of them pass. The final test yield is 441 ÷ 450, or 98%. Overall, 441 of the original 500 chips can ship, so the overall yield is about 88%.

So the overall yield is the pass rates of each stage multiplied together (0.9 × 0.98 ≈ 0.88). By seeing which stage loses the most chips, you can tell roughly which step needs fixing. You can explore how chip size relates to yield with the die per wafer and yield calculator.

Common myths

By the numbers

One wafer yields hundreds of chips, and each one gets its own electrical test. Assembly and test alone take weeks. The price of a chip includes all of this testing work.

Learn more

• Explainers on the process: "How Are Chips Made?", "What Is a Silicon Wafer?", "What Is Semiconductor Packaging?"
• Comparison tables: "Wafer Test vs Final Test", "Scan Test vs BIST", "HTOL vs THB vs HAST vs TC vs HTS"
• Glossary terms in depth: ATPG (creating test values automatically) / fault coverage / KGD (especially important for "chiplets," which combine several chips)
• Careers: testing and yield each have their own specialists, called test engineers and yield engineers.