What Is CMP in Semiconductors? Chemical Mechanical Polishing

In everyday life

The chip in your smartphone is not one flat circuit. Tiny switches called transistors sit at the bottom. On top of them are many stacked layers of wiring that connect them. For example, Intel says its "Intel 4" manufacturing technology, presented in 2022, stacks 16 layers of wiring.

Each time a layer is added, its surface becomes bumpy. If the next layer goes on top as is, the bumps keep growing. So after each layer, the surface is polished flat again. This polishing step is CMP.

CMP stands for chemical mechanical polishing. It is sometimes said to stand for chemical mechanical planarization, where "planarization" means making flat.

Why does the surface have to be flat?

The first reason lies in exposure, the step that prints the circuit pattern with light. The exposure tool uses lenses or mirrors to shrink the pattern and project it onto the wafer surface. The pattern prints sharply only within a narrow band of height. It is like taking a close-up photo: things slightly in front or behind look blurred.

This range of height that is in focus is called the depth of focus. The finer the patterns a tool can print, the narrower this range gets. If bumps remain on the surface, the low spots or the high spots fall out of focus. Then the pattern blurs there. "What Is EUV Lithography?" also explains how focus works.

The second reason is the stacking of wiring layers. Connecting billions of transistors takes many layers of wiring, piled one on another. This structure is called a multilevel interconnect. If bumps in a lower layer remain, the steps grow with every layer on top. They can also make wires break, or connect where they should not.

Ebara Corporation makes CMP tools. According to Ebara, the height differences on the surface after CMP are 10–20 nm. A nanometer (nm) is one millionth of a millimeter. The flatness of the wafer itself is covered in "What Is a Silicon Wafer?"

How CMP works: press down and spin

At the heart of a CMP tool is a large, round, spinning table. This table is called the platen, and a polishing pad is stuck to its surface. The pad is made of resin, a kind of plastic, and its surface is full of tiny pores.

The wafer is mounted on a part called the polishing head, with its circuit side facing down. The head presses the wafer onto the pad while spinning, and the platen below spins too. Meanwhile, a polishing liquid is poured on from above, nonstop.

The liquid is called slurry. It is water mixed with nanometer-sized particles and with chemicals that react with the surface. The particles are often silica (silicon dioxide), the main ingredient of glass. Each type of film has its own slurry, with a different mix of particles and chemicals.

As polishing goes on, the pad's surface clogs up and turns smooth. So a tool coated with diamond grains shaves the pad surface little by little to make it rough again. This upkeep is called pad conditioning. It matters because a pad in uneven condition changes how fast material is removed.

Chemistry loosens, mechanics removes

The "chemical" and "mechanical" in CMP's name do different jobs. First, the chemicals in the slurry react with a very thin top layer of the film. The reacted layer is softer than the original film and comes off more easily. On a metal film, the surface turns into something like a thin layer of rust.

Next, the slurry particles and the pad scrub away only that softened layer. A fresh surface appears underneath and reacts with the chemicals again. This cycle of "loosen" and "remove" repeats nonstop, in extremely thin steps. Little by little, it wears the surface down.

There is a reason to combine the two. With chemicals alone, the high spots and the low spots dissolve alike, so the surface never gets flat. With particles alone, hard films barely wear down, and rubbing harder leaves scratches. Together, even fine particles remove material quickly while keeping scratches down.

So why do the high spots wear down first? When the wafer is pressed onto the pad, the pad pushes hardest on the high points of the surface. Where the pressure is higher, material comes off faster, so the high spots drop first. As the gap between high and low shrinks, the whole surface finally becomes flat.

Copper wiring is made by "filling, then polishing"

Besides flattening, CMP has another important job: shaping copper wiring. For a long time, the metal in chip wiring was aluminum. In 1997, IBM announced a chip that used copper wiring. Copper conducts electricity better, which cuts signal delay and heat ("What Is a Resistor?").

Copper, however, is hard to shape in the usual way. That way coats the whole surface with a metal film, then uses gases to remove the parts that are not needed. When copper reacts with those gases, the products do not easily turn into gas, so they stay on the surface. So the order of the steps was reversed.

First, trenches in the shape of the wiring are dug into a film that does not conduct electricity (an insulating film). Next, copper is added until it overflows the trenches. Finally, CMP polishes away the copper that spilled outside the trenches. Copper stays only inside them, forming the individual wires. This method is called the damascene process.

The name comes from damascening, a craft in which grooves are carved into a metal surface and another metal is inlaid into them. Before copper fills the trenches, a thin film of another metal is laid down. It keeps copper from seeping into the surroundings (barrier metal). CMP also removes this film outside the trenches. For how this differs from shaping wires by etching with gases, as is done with aluminum, see "Damascene vs Subtractive Etch Interconnects."

In practice, a common method makes both the trenches and the vertical holes that reach the layer below. Then it fills and polishes them with copper in one go. The plating step that fills the trenches with copper, and how films are added in general, are left out here.

Preventing over-polishing: dips and knowing when to stop

In copper CMP, the soft copper wears away more easily than the insulating film around it. The pad flexes a little, so in a wide line the copper in the middle sinks like a dish. This is called dishing. The wider the line, the deeper the dip.

Where many thin lines are packed closely together, something else happens. The insulating film between them is polished away along with the copper. The whole area ends up lower than its surroundings. This is called erosion, and it gets worse the more densely the lines are packed. Both thin the wires, so current flows less easily, and both spoil the flatness for the next layer.

So steps are taken from the chip design stage. Designers set a maximum width for lines. They also add "dummy" patterns, which have no electrical use, to areas with few wires. Then the wiring density is similar everywhere on the chip, so it polishes evenly. In this way, CMP affects not only manufacturing but also the design rules.

Another key point is knowing when to stop. Too little polishing leaves neighboring wires still connected. Too much makes the dips worse. So the surface is measured during polishing, to find the moment the target film appears. This is called endpoint detection.

For example, one method shines light on the wafer. It estimates the remaining film thickness from changes in the color of the reflected light. For metal films, another method uses a magnetic sensor to check how much metal is left.

Cleaning right after polishing

After polishing, the wafer surface still carries slurry particles, polishing debris and chemicals. If the wafer moves on to the next step like this, they cause defects. So the wafer is cleaned right after CMP.

A typical method scrubs the wafer with soft, sponge-like brushes while spraying it with a cleaning liquid. The key is to clean the wafer before it dries. Once slurry dries, the particles stick to the surface and are hard to remove.

Polishing makes particles and debris, so it is not a natural fit for a room kept free of dust (a cleanroom). In the early 1990s, Ebara developed a tool that polishes, cleans and dries the wafer all in one machine. This made it possible to put CMP tools inside the cleanroom. Today's main CMP tools also polish, clean and dry in one unit ("What Is a Cleanroom?").

Where did CMP come from?

Polishing glass and lenses to a mirror finish with a liquid full of fine particles is an old technique. Silicon wafers, too, are polished to a mirror finish with particles and chemicals before they are shipped. But polishing a wafer partway through building circuits was harder in a new way. The surface mixes films of many materials, and polishing must stop at exactly the right layer.

IBM put this into practical use as a chipmaking step in the 1980s. At the time, adding more wiring layers made the bumps bigger. Then the surface no longer fit within the range of height that exposure keeps in focus. That was the barrier.

In the 1990s, equipment makers began selling CMP tools, and CMP spread to chip factories. Ebara delivered its first CMP tool in 1992. When copper wiring arrived in 1997, CMP became essential not just for flattening but also for shaping the wiring.

Recently, CMP is also used in technologies that stack chips and bond them together. If the surfaces to be bonded are even slightly uneven, gaps form and the connections fail. The bonding methods are compared in "Hybrid Bonding vs Microbumps."

The part that encloses a chip and connects it to a circuit board is called the package. In September 2025, Ebara joined a group that develops next-generation packages together. Ebara says it joined to improve its CMP tools for polishing large rectangular panels.

Who makes it?

The main makers of CMP tools are Applied Materials in the US and Ebara in Japan. How they relate to other chipmaking tools is covered in "Semiconductor Manufacturing Equipment."

Slurries and pads come from separate materials makers. Among them are Fujimi Incorporated and Resonac in Japan, and Entegris and Qnity Electronics in the US. This field has seen many mergers and spin-offs, so older documents may use other company names. Resonac was formed in January 2023 by combining Showa Denko and the former Hitachi Chemical. Qnity split off from DuPont in November 2025. Entegris acquired CMC Materials, a maker of CMP materials, in July 2022.

Common misconceptions

By the numbers

Ebara's comparison shows how hard CMP is. The Yamanote line is a railway that runs in a loop around central Tokyo. Picture leveling all the land inside that loop until the height differences are only about 0.5 mm. On top of that, the surface is a fine pattern of copper and insulating film, which differ in hardness. And it has to be polished again every time a layer is added.

Learn more

• Where it fits in the whole process: "How Are Chips Made?", "Semiconductor Manufacturing Equipment"
• Compare in a table: "Damascene vs Subtractive Etch Interconnects", "Copper vs Cobalt vs Ruthenium Interconnects" (metals for very thin wires), "STI vs LOCOS Isolation" (ways of separating transistors, including one that uses CMP)
• Try the numbers: the lithography resolution calculator shows how the in-focus range (depth of focus) narrows as patterns get finer. With the interconnect RC delay calculator, you can see how signal delay changes when wires get thinner.
• See it in figures: diagrams of a CMP tool's layout and of the damascene flow are in the list of figures.