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Static vs Dynamic vs Wafer-Level Burn-In: Differences Explained

Burn-in is a screen that powers products at high temperature and above their rated voltage to remove units prone to early failure before shipment. Static burn-in only applies power and fixed bias without operating the circuit, so the equipment is simple, but stress reaches only limited parts. Dynamic burn-in applies clocks and test patterns to operate the internal circuits, so stress reaches a wider area. Wafer-level burn-in differs in the stage at which it is done: stress is applied to the whole wafer before dicing, finding defective chips before they are packaged.

AspectStatic burn-inDynamic burn-inWafer-level burn-in
How stress is appliedOnly supply voltage and fixed bias are applied at high temperature. The circuit is not operatedAt high temperature and high voltage, clocks and test patterns are applied, operating the circuit while toggling internal nodes between 0 and 1Power and signals are applied at once to many chips on the wafer through contactors
StageAfter packagingAfter packagingBefore dicing (in wafer form)
Typical conditionsAbout 125 °C, supply voltage above rated, for a few hours to a few tens of hoursAbout 125 °C, supply voltage above rated, for a few hours to a few tens of hoursThe same idea of acceleration by temperature and voltage. Conditions are set for the product and equipment
Stress coverageLimited to parts biased by the fixed inputs; many internal nodes stay in fixed statesOperating the internals with scan, BIST and similar means stresses more transistors and interconnectsDepends on the method: some apply only power and bias, others operate the chip using on-chip self-test circuits and similar means
Defects easily foundVoltage-accelerated defects in biased parts, such as weak spots in oxides and junction leakageEarly failures can be found more comprehensively, including in parts stressed only during operationChips that would fail early can be found before packaging
Equipment and fixturesSimple: burn-in boards, oven, power supplyRequires boards with signal-generating drivers and the equipment for themRequires dedicated contactors that contact the entire wafer surface and dedicated equipment, which are expensive
Operation monitoringUsually none. Pass/fail is judged by electrical testing after burn-inSome methods monitor the outputs during burn-inDepends on the method
CostLowHigherFixtures and equipment are expensive, but defective chips do not have to be packaged
Main challengesLow stress coverageIn high-power products, heat generation is large and temperature control is difficultReliable contact with many chips, power capacity and heat across the whole wafer, isolating defective chips
Typical usesProducts with simple structures, or where voltage stress is the main concernHigh-reliability products for automotive and servers, such as logic ICs, memory and processorsMulti-chip packages that need known good die (KGD), stacked memory, products shipped as bare die

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Static burn-in
For products where the main defects can be accelerated by voltage stress without operating the circuit, when you want to keep equipment and cost down.
Dynamic burn-in
When you want more reliable screening of products with complex internal circuits, where many parts receive no stress unless the circuit is operated.
Wafer-level burn-in
When you need die confirmed good before packaging (KGD), such as packages stacking multiple chips, where one defective chip makes the whole package defective.
Place in the test flow
The usual flow is wafer test, assembly, final test, then shipment, and package burn-in is inserted before or after final test. Wafer-level burn-in applies stress at the wafer test stage.

FAQ

What is the difference between static and dynamic burn-in?

Static burn-in only applies power and fixed bias without operating the circuit. Dynamic burn-in operates the circuit, toggling internal nodes with clocks and test patterns, so it stresses more transistors and interconnects and finds early failures more easily.

Why is burn-in done in wafer form?

When multiple chips go into a single package, even one defective chip makes the whole package defective. Burning in at the wafer level and removing chips that would fail early lets you assemble only die confirmed good (KGD).

Doesn't burn-in shorten the life of good units?

It uses up a little, but conditions are chosen so that good units lose only a tiny fraction of their wear-out life. The purpose of burn-in is to get through the early failure period of the bathtub curve before shipment, so that products ship in the low-failure-rate random failure period.

Check your understanding

Which correctly describes the purpose of burn-in?

  1. ATo inspect the appearance of chips
  2. BTo apply stresses such as high temperature and voltage to remove products prone to early failure before shipment
  3. CTo measure film thickness on wafers
Show answer and explanation

Answer: B. To apply stresses such as high temperature and voltage to remove products prone to early failure before shipment

Burn-in operates products for hours to tens of hours at around 125 °C and above-nominal voltage, forcing latent defects to fail early so those parts can be screened out. The aim is to get through the infant-mortality portion of the bathtub curve before shipment, and it is applied to high-reliability products such as automotive and server parts. It differs in purpose from visual inspection or film-thickness measurement.

Which correctly lists the three periods that make up the bathtub curve, showing how failure rate changes over time?

  1. AEarly failure period, random failure period, wear-out failure period
  2. BDesign period, manufacturing period, shipping period
  3. CPrototype period, mass production period, maintenance period
Show answer and explanation

Answer: A. Early failure period, random failure period, wear-out failure period

The bathtub curve has three periods shaped like a bathtub cross-section: infant mortality, with high failure rates from manufacturing defects early in use; the random-failure period, with low and nearly constant rates; and wear-out, where degradation raises the rate. Infant failures are screened out before shipment by burn-in, and products are designed so wear-out begins after their intended life. Design, manufacturing and shipping are lifecycle stages, not failure-rate periods.

What is KGD (Known Good Die), which is important when mounting several chips in one package?

  1. AA large chip
  2. BA failed chip
  3. CA chip (die) confirmed to be good before mounting
Show answer and explanation

Answer: C. A chip (die) confirmed to be good before mounting

When multiple chips go into one package, a single bad die scraps the whole package, including the good dies. Stacking eight dies that are each 99% good gives only 0.99⁸ ≈ 92% chance that all are good. It is therefore essential to use thoroughly tested known good dies (KGD) before assembly, a point especially important for HBM and chiplets.

  1. Which correctly describes the typical test flow of semiconductor products?
  2. In accelerated tests that raise temperature to shorten life test time, which model is often used to express the relationship between temperature and lifetime?
  3. Which typical reliability test evaluates lifetime and failure rate by operating products at high temperature for a long time?

Practice Testing and inspection questions

Key terms explained

Burn-in
A test that operates products under stress such as high temperature and high voltage to remove units prone to early failure before shipment.
Bathtub curve
A curve showing how the failure rate changes over time. It consists of the early-failure, random-failure and wear-out periods and is shaped like a bathtub.
KGD (known good die)
A chip confirmed to be good before packaging. It matters when several chips go into one package, because a single bad chip ruins the whole module.
Arrhenius model
A model in which reaction or degradation rates vary with temperature as exp(−Ea/kT). It is used to estimate lifetime at operating temperature from accelerated tests at higher temperatures.
Wafer test (probe test)
Checking the electrical characteristics of each chip on the wafer by touching probes to its pads before dicing. It finds bad chips before assembly so they are not packaged needlessly.

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