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Scan Test vs BIST: Key Differences Explained

Scan test connects the flip-flops in a chip into shift registers (scan chains), shifts test patterns in from an external tester, and shifts out the circuit's responses to compare them with expected values. The patterns are generated from the netlist by ATPG tools. BIST builds a circuit that generates patterns and a circuit that checks results into the chip, so that the chip tests itself. In production test, it is common to combine scan test for logic with memory BIST for embedded memories, and BIST can also be used for self-diagnosis after shipment.

AspectScan testBIST (built-in self-test)
Basic ideaFlip-flops are connected into scan chains; a pattern is shifted in, the circuit is clocked once, and the result is shifted out and comparedCircuits that generate patterns and check responses are built into the chip, which tests itself and reports pass or fail
How test patterns are generatedATPG creates deterministic patterns from the netlist that target stuck-at and transition delay faultsLogic BIST generates pseudo-random patterns with an LFSR. Memory BIST generates addresses and data using fixed procedures such as March tests
Response checkingThe tester compares responses with expected values (with test compression, responses compressed on chip are compared)Logic BIST compresses responses with a MISR into a signature that is compared with an expected value. Memory BIST checks read values directly with comparators
Dependence on the testerPatterns and expected values are held in tester memory. Requires scan pins plus tester performance and memory capacityOnly starting the test and reading the result (via JTAG, etc.) are needed, so a simple tester suffices
Main targetsLogic circuits (combinational logic and flip-flops)Memory BIST: embedded memories such as SRAM. Logic BIST: logic circuits
Fault coverageEasy to make high because patterns are generated for the targeted faultsLogic BIST tends to leave faults that are hard to detect with pseudo-random patterns, which test point insertion compensates for. Memory BIST achieves high coverage with procedures tailored to memory fault models
Added circuitryFlip-flops are replaced with scan flip-flops (with a selection multiplexer), and chain wiring is addedRequires a pattern generator, a response compactor and a control circuit. Logic BIST also requires preparing the design so that no unknown values (X) occur
Test timeLong chains take time to shift, and speed is also limited by the tester. Test compression shortens itMany patterns can run quickly with on-chip clocks. Logic BIST needs a large number of patterns
When it is usedMainly in production wafer test and final test. Also used for failure diagnosis of defective partsIn addition to production test, it can also be used for inspection after board mounting and for self-diagnosis after shipment, such as at power-on

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Scan test
When you want to find structural logic faults with high coverage in production test, or to narrow down the fault location in a failed chip.
BIST
Testing embedded memories that are hard to access directly from outside. When you want to reduce tester pins or memory. When self-diagnosis after shipment is needed at power-on or before driving, as in automotive applications.
Combined
Real chips commonly use scan test (with test compression) for logic and memory BIST for memories. Logic BIST also runs on top of the scan chains.

FAQ

If a chip has BIST, is scan test unnecessary?

Many chips use both. Logic BIST uses pseudo-random patterns, so hard-to-detect faults tend to remain, and production test typically secures high fault coverage with scan test using ATPG-generated patterns. Memories have a regular structure, so they are tested with memory BIST.

How are logic BIST and scan test related?

Logic BIST also uses scan chains. Patterns generated by an LFSR are shifted into the chains, the circuit is clocked, the responses that come out are compressed by a MISR, and the final signature is compared with an expected value. It is built on a scan design.

Why is BIST widely used to test embedded memories?

Because memories embedded in a chip are hard to read and write directly from external pins, and their regular structure lets a small circuit generate addresses and data in fixed sequences such as March tests. It is also often combined with repair that replaces failing bits with spare rows or columns.

Why do automotive chips run BIST at power-on?

To find faults that arise after shipment and latent faults that do not show up in normal operation. BIST can run on the chip itself without a tester, so it can be used for self-diagnosis inside the vehicle.

Check your understanding

Which correctly describes scan design, a form of design for testability (DFT)?

  1. AScanning the chip surface with an optical microscope to find defects
  2. BGradually raising the supply voltage during test to find the operating limit
  3. CConnecting the flip-flops in a circuit like a shift register to make it easy to set and observe internal states
Show answer and explanation

Answer: C. Connecting the flip-flops in a circuit like a shift register to make it easy to set and observe internal states

Scan design adds a multiplexer at each flip-flop input; in test mode the flip-flops are chained into scan chains so arbitrary values can be shifted in and internal values shifted out. This turns sequential-circuit testing into combinational-circuit testing, letting ATPG automatically generate patterns with high fault coverage. It has nothing to do with microscope scanning or voltage sweeps.

Which correctly describes BIST (built-in self-test)?

  1. AAll tests are performed by an external tester alone
  2. BTest circuitry is built into the chip so that the chip tests itself
  3. CAppearance is inspected by eye
Show answer and explanation

Answer: B. Test circuitry is built into the chip so that the chip tests itself

BIST builds pattern-generation and result-checking circuits into the chip so it can test itself. Memory BIST generates patterns such as March tests at speed, while logic BIST uses pseudo-random patterns. It reduces dependence on expensive testers and test time, and in automotive chips it enables self-diagnosis in the field, for example at every power-up.

What is it called to automatically generate test patterns that detect faults from a circuit's netlist?

  1. ADRC
  2. BATPG (automatic test pattern generation)
  3. CCTS
Show answer and explanation

Answer: B. ATPG (automatic test pattern generation)

ATPG automatically generates, from the netlist, input patterns that activate each modeled fault (such as stuck-at faults) and propagate its effect to an output. Combined with scan design, it efficiently produces high-coverage patterns even for circuits of hundreds of millions of gates. DRC checks layout design rules and CTS synthesizes clock trees; both are design steps.

  1. Which is the correct definition of fault coverage for test patterns?
  2. What is the technology called that expands test patterns inside the chip and compresses the responses to reduce scan test data volume and test time?
  3. What is the main functional safety purpose of running logic BIST and memory BIST in an automotive microcontroller at power-up or before driving?

Practice Testing and inspection questions

Key terms explained

Scan test
A test method that uses scan chains, formed by linking a circuit's flip-flops in series, to set and observe internal states.
BIST (built-in self-test)
Test circuitry built into the chip so that it generates test patterns and checks results by itself. It is widely used, for example, to test memories.
ATPG (automatic test pattern generation)
Automatically generating test patterns that detect faults from a circuit's netlist. It is used together with scan design.
Fault coverage
The fraction of modeled faults that a set of test patterns can detect. The higher it is, the less likely defective chips are to escape.
DFT (design for testability)
A design approach that builds test features such as scan chains and BIST into the circuit in advance.

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