Enter the activity factor, total switched capacitance, supply voltage, clock frequency and leakage current to calculate the dynamic and static power of a CMOS circuit. You can also see how far the total power falls when DVFS lowers the voltage and frequency by the same ratio.
Results
Dynamic power αCV²f
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Static power Ileak × V
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Total power
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Static share
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Total power after DVFS
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Power after DVFS (% of original)
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Dynamic power is P = αCV²f, with α the probability per clock cycle that a node switches from 0 to 1 (texts that define α as the fraction of all transitions write ½αCV²f). Static power is estimated as Ileak × V; in the DVFS estimate the leakage current itself is assumed independent of voltage, so only the × V factor scales. Short-circuit power is not included.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
What αCV²f means
Each time a CMOS gate output rises from 0 to 1, the load capacitance C draws CV² of energy from the supply. Half is lost as heat in the pMOS while charging, and the half stored on the capacitor is dissipated in the nMOS on the next 1-to-0 transition. If α is the probability of a 0-to-1 transition per clock cycle, dynamic power is P = αCV²f. With the defaults of α = 0.1, C = 1 nF, V = 1.0 V and f = 2 GHz, P = 0.1 × 10⁻⁹ × 1² × 2 × 10⁹ = 0.2 W.
Static power and its share
Even when transistors are off, current keeps flowing as subthreshold current, tunneling through the thin gate dielectric and junction leakage. The resulting static power is estimated here as Ileak × V. With the defaults it is 100 mA × 1.0 V = 0.1 W, or 33.3% of the 0.3 W total. Subthreshold current grows exponentially as the threshold voltage is lowered and rises steeply with temperature. Because scaling pushed threshold voltages down, static power became a significant part of the total.
Why DVFS saves so much
Lowering the supply voltage slows the logic, so a lower frequency allows a lower voltage. Scaling both by s multiplies dynamic power, which goes as V²f, by s³. At 80% with the defaults, dynamic power falls by 0.8³ = 0.512 to about 0.102 W and static power to 0.08 W, for a total of 0.1824 W, or 60.8% of the original. A fixed task now takes 1/s times longer, though, so its dynamic energy falls only by s². When static power is large, running slowly also wastes more leakage energy.
How designs reduce power
Each term in the formula maps to a power-saving technique. Clock gating stops the clock to idle logic and lowers α; shorter wires and smaller transistors reduce C. Voltage acts as a square, so it has the largest effect, and DVFS, which adjusts voltage and frequency to the load, is widely used. For static power, power gating switches off idle blocks, and high-threshold transistors are used on paths that do not need speed. Being unable to lower the threshold voltage further without excessive leakage is a major reason supply voltages stopped falling.
BThe fraction of signals switching per clock cycle (the activity factor)
CThe chip temperature
Show answer and explanation
Answer: B. The fraction of signals switching per clock cycle (the activity factor)
Dynamic power is consumed charging and discharging the capacitance of wires and gates. C is the switched capacitance, V the supply voltage, f the clock frequency and α the activity factor, the fraction of signals that switch per clock. Parts whose data does not change, or whose clocks are stopped, do not switch, so reducing α is also an important power-saving lever.
Substituting into P = αCV²f gives 0.1 × 1 × 10⁻⁹ F × (1 V)² × 1 × 10⁹ Hz = 0.1 W. The nano (10⁻⁹) of the capacitance and the giga (10⁹) of the frequency cancel, which keeps the arithmetic simple. In real chips the switched capacitance grows with circuit size, and total dynamic power can reach tens to hundreds of watts.
APower falls to one-eighth and energy to one-quarter
BBoth power and energy halve
CPower falls to a quarter and energy is unchanged
Show answer and explanation
Answer: A. Power falls to one-eighth and energy to one-quarter
Power is proportional to V²f, so halving both V and f gives (1/2)² × 1/2 = 1/8. The computation takes twice as long, so energy is 1/8 × 2 = 1/4. Equivalently, since energy per switching event is proportional to CV², energy scales with the square of voltage. In practice the voltage range is limited and static power exists, so the reduction is not this ideal.
Dynamic power is proportional to the square of voltage, so scaling voltage by 0.9 scales power by 0.9² = 0.81, a reduction of about 19%. Even small voltage changes have a large effect on power, making voltage reduction one of the most effective power-saving levers. Lower voltage slows circuits, though, so it must stay within the range that keeps required speed, and doing this according to load is what DVFS does.
FAQ
How much does dynamic power drop if the supply voltage is lowered by 10%?
Dynamic power scales with the square of the voltage, so at the same frequency it becomes 0.9² = 0.81 times, a drop of about 19%. If the frequency is also lowered by 10%, it becomes 0.9³ ≈ 0.73 times, a drop of about 27%.
Which is correct, P = αCV²f or P = ½αCV²f?
Both, with different definitions of α. If α is the probability of a 0-to-1 transition per clock cycle, P = αCV²f. If α counts both rising and falling transitions, each one dissipates ½CV², so P = ½αCV²f. Check which meaning a problem uses.
How can static power be reduced?
Power gating idle blocks, using high-threshold transistors, lowering the supply voltage and keeping the chip cooler all help. Clock gating reduces dynamic power and does not cut leakage current.