Logic circuits

Which correctly describes the hold time of a flip-flop?

  1. AThe time the data input must be stable before the active clock edge
  2. BThe time from the clock edge until the output changes
  3. CThe time the data input must remain unchanged after the active clock edge
Show answer and explanation

Answer: C. The time the data input must remain unchanged after the active clock edge

Hold time is the minimum time the data must remain stable after the clock edge. The time it must be stable before the edge is the setup time. Hold violations cannot be fixed by slowing the clock, so they are addressed by, for example, adding delay to the data path.

  • A. The time the data must be stable before the edge is the setup time.
  • B. The time from clock to output is the clock-to-Q delay.
  • C. Correct. It is the time the data must be held after the edge.
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