Cache address breakdown and average memory access time
Enter the cache size, line size and associativity to see how an address splits into tag, index and offset, shown as bit counts and a bar. The calculator also computes the average memory access time (AMAT) from hit time, miss rate and miss penalty, so you can see how the cache organization affects performance.
Results
Address breakdown (most significant bits on the left)
Enter powers of two for the cache size, line size and associativity, with the size divisible by line size × ways. The split also cannot be computed when the offset and index bits together exceed the address width.
Lines
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Sets
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Tag
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Index
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Offset
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Average memory access time (AMAT)
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See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
Splitting an address into three fields
A cache holds main-memory data in units called lines (blocks). The number of lines is size ÷ line size, and the number of sets is lines ÷ associativity. From the low end of the address, the offset selects a byte within the line and takes log₂(line size) bits, the index selects a set and takes log₂(sets) bits, and the remaining upper bits form the tag. With the defaults of 32 bits, 32 KB, 64 B and 8 ways, there are 512 lines and 64 sets, giving a 6-bit offset, a 6-bit index and a 32 − 6 − 6 = 20-bit tag.
What associativity changes
Doubling the associativity at the same size and line size halves the number of sets, so the index loses one bit and the tag gains one. One way is a direct-mapped cache, and setting the ways equal to the number of lines (512 with the defaults) gives a fully associative cache with a single set and a 0-bit index. Higher associativity reduces conflict misses caused by addresses crowding into the same set, but more tags must be compared in parallel, which costs comparator area, power and hit time.
Average memory access time (AMAT)
Caches should be compared by average memory access time, not miss rate alone. AMAT = hit time + miss rate × miss penalty, which is 4 + 0.05 × 100 = 9 cycles with the defaults. Even a 5% miss rate more than doubles the average because the penalty is large. Lowering the miss rate with a larger or more associative cache does not help if the hit time grows, since every access pays it. For multilevel caches, replace the L1 miss penalty with the L2 hit time + L2 miss rate × L2 miss penalty.
Design use and pitfalls
Larger lines exploit spatial locality and lower the miss rate, but each miss moves more data, raising the miss penalty, and fewer lines mean more conflicts; most current CPUs use 64 B. L1 caches often use a virtually indexed, physically tagged (VIPT) design that reads the set while the TLB translates the address. Keeping the index and offset inside the page offset limits the size to page size × associativity, for example 4 KB × 8 ways = 32 KB. The tag width also sets the size of the tag storage.
A 64-byte line = 2⁶, so the offset is 6 bits. The number of lines is 32 KB ÷ 64 B = 32,768 ÷ 64 = 512 = 2⁹, and in a direct-mapped cache each line is its own set, so the index is 9 bits. The rest is the tag: 32 − 9 − 6 = 17 bits. 19 bits would apply to a 4-way set-associative cache, where the index shrinks by 2 bits, not to a direct-mapped one.
The number of lines is 32 KB ÷ 64 B = 512. A 4-way cache holds four lines per set, so there are 512 ÷ 4 = 128 = 2⁷ sets, giving a 7-bit index and a 32 − 7 − 6 = 19-bit tag. 512 is the line count itself, which equals the set count only when direct-mapped. Raising associativity reduces the number of sets, which adds tag bits and comparators. 32 comes from wrongly dividing the 64-byte line size by the number of ways.
Average memory access time = hit time + miss rate × miss penalty = 2 + 0.04 × 150 = 2 + 6 = 8 cycles. The hit time applies to every access, and the miss penalty is added only on misses. 6 cycles omits the hit time, counting only the misses. 152 cycles is the time for a single access that misses, not the average. Even a 4% miss rate quadruples the average.
The offset is the low 6 bits (64 = 2⁶), and the index is the next 6 bits (64 sets = 2⁶). 0x1234 = 4,660, and 4,660 ÷ 64 = 72 remainder 52, so the line number is 72. The set number is the line number modulo the set count: 72 mod 64 = 8. 52 is the remainder, the position within the line (offset). 4 is merely the last hexadecimal digit of the address and has nothing to do with the set.
FAQ
How many tag bits does a direct-mapped 32 KB cache with 64 B lines and 32-bit addresses have?
The offset is log₂64 = 6 bits, and 32 KB ÷ 64 B = 512 lines gives a 9-bit index, so the tag is 32 − 9 − 6 = 17 bits. Making it 8-way reduces the sets to 64, giving a 6-bit index and a 20-bit tag.
How many index bits does a fully associative cache have?
Zero. There is only one set, so every bit except the offset is tag, and the tag is compared against every line. You can check this here by setting the associativity equal to the number of lines.
Which helps more, halving the miss rate or cutting the hit time by one cycle?
With the defaults (4-cycle hit time, 5% miss rate, 100-cycle miss penalty), a 2.5% miss rate lowers AMAT from 9 to 6.5 cycles, while a 3-cycle hit time gives 8 cycles, so the miss rate matters more here. With a small miss penalty the answer can flip, so compare using the AMAT formula.