ISA & Assembly

In the RISC-V conditional branch "beq a0, a1, label", how is the target address of label encoded?

  1. AThe full 32-bit target address is held in the instruction
  2. BAs a distance from the address (PC) of the branch instruction itself, held in the instruction
  3. CThe target address must be placed in register a1 beforehand
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Answer: B. As a distance from the address (PC) of the branch instruction itself, held in the instruction

RISC-V branches encode the target as a signed distance in bytes from the address (PC) of the current instruction. This is called PC-relative addressing. Branch targets are usually nearby, so a short distance suffices and fits within the 32-bit instruction. And because the distance stays the same if the whole program is placed at another address, the code works without being rewritten.

  • A. A 32-bit address cannot fit in a 32-bit instruction.
  • B. Correct. This is PC-relative addressing.
  • C. a1 is one of the values compared, not an address.
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More ISA & Assembly questions

  1. What is an advantage of using PC-relative addressing for branches and jumps?
  2. Which statement about instruction length in the RISC-V base ISA and in x86 is correct?
  3. What is the main advantage of making instructions a fixed length?
  4. In RISC-V instructions, each register field (rd, rs1, rs2) is 5 bits wide. Why?
  5. The immediate of RISC-V addi is a 12-bit signed integer. What range can it represent?