ISA & Assembly

On 64-bit RV64I, how does lw place the 32-bit value it loads into a 64-bit register?

  1. AThe upper 32 bits keep their old value and only the lower 32 bits change
  2. BIt is always zero-extended to 64 bits
  3. CIt is sign-extended to 64 bits (lwu is used for zero extension)
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Answer: C. It is sign-extended to 64 bits (lwu is used for zero extension)

On RV64I, lw sign-extends the 32-bit value into the 64-bit register, while lwu, the unsigned load, fills the upper bits with zeros. Leaving the old upper bits in place would create a dependence on the previous value and hinder out-of-order execution, so RISC-V never does that. For 32-bit arithmetic there are instructions with a "w" suffix such as addw, which compute a 32-bit result and then sign-extend it.

  • A. RISC-V never leaves the old upper bits in place.
  • B. Zero extension is the lwu instruction.
  • C. Correct. It treats the value as a signed 32-bit number.
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