ISA & Assembly

The standard RISC-V calling convention requires sp to be a multiple of 16 bytes on function entry. What is the main reason?

  1. ABecause the OS will not boot unless the stack size is a multiple of 16 bytes
  2. BBecause the low 4 bits of sp record the function number
  3. CSo that data up to 16 bytes placed on the stack can be accessed efficiently without crossing alignment boundaries
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Answer: C. So that data up to 16 bytes placed on the stack can be accessed efficiently without crossing alignment boundaries

Data placed at an address that is a multiple of its size (aligned) can be accessed in one operation without crossing a boundary. Keeping sp a multiple of 16 preserves alignment for 8-byte doubles or 16-byte long doubles placed on the stack. So functions allocate frames in multiples of 16 bytes, using "addi sp, sp, -16" even if they save only one register.

  • A. It has nothing to do with booting the OS.
  • B. No information is stored in the low bits of sp.
  • C. Correct. It keeps double-precision and 128-bit data aligned.
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More ISA & Assembly questions

  1. The code above is the start (prologue) of a function. What does it do?
  2. What is an advantage of using a frame pointer (s0/fp in RISC-V) inside a function?
  3. In RISC-V, what happens if a recursive function (one that calls itself) forgets to save ra on the stack?
  4. On little-endian RISC-V, a register holding 0x12345678 is stored with sw to address 0x100. What value does lbu then read from address 0x101?
  5. In RISC-V, what can happen when the address of a 4-byte lw is not a multiple of 4 (misaligned)?