ISA & Assembly

What does the RISC-V instruction "slt t0, a0, a1" do?

  1. AShifts a0 left by a1 bits and puts the result in t0
  2. BBranches to the address in t0 if a0 is less than a1
  3. CPuts 1 in t0 if a0 is less than a1, otherwise 0
Show answer and explanation

Answer: C. Puts 1 in t0 if a0 is less than a1, otherwise 0

slt (set less than) compares two registers as signed integers and writes 1 if the first is smaller, otherwise 0. There are also sltu for unsigned comparison and slti for comparison with an immediate. It is used when a comparison result is needed as a value, as in C's "x = (a < b);", or to replace a branch with arithmetic. Shifts are sll and branches are separate instructions such as blt.

  • A. Shift left is the sll instruction.
  • B. slt does not branch.
  • C. Correct. It stands for set less than.
Practice this topic Back to topic

More ISA & Assembly questions

  1. When the RISC-V code above finishes, what is the value in t0?
  2. RISC-V conditional branches (B-type) encode the distance as a 13-bit signed byte offset whose lowest bit is always 0 and not stored. Roughly what range can a branch reach directly?
  3. What does the RISC-V instruction "jal ra, func" do?
  4. Which real instruction executes the RISC-V pseudo-instruction "ret"?
  5. What is the main purpose of defining a calling convention?