What Is RISC-V? The Open Instruction Set Explained
RISC-V (pronounced "risk-five") is an instruction set. It defines which instructions a CPU can run and how each one is written in 0s and 1s. Its key feature is that the specification is public. Anyone can design and sell a CPU that follows it without paying a license fee. It started in 2010 at the University of California, Berkeley. Today it is widely used in microcontrollers and in the small CPUs that run things inside a GPU.
What you'll learn
- What an instruction set is, and why it is a "contract" between software and the CPU
- How x86, Arm and RISC-V differ (especially who may build CPUs, and how they pay)
- How RISC-V works as "a small base plus extensions you choose"
- Where it is used, what "free" really means, and its open problems
Prerequisites: it helps to know that a CPU is "the part that runs simple instructions, written in 0s and 1s, one at a time."
In everyday life
Hobbyists often use small microcontroller boards with built-in Wi-Fi. In some of these products, the CPU follows an instruction set called RISC-V. NVIDIA's GPUs also contain small CPUs that follow RISC-V. Makers of hard drives and SSDs have announced plans to switch their control CPUs to RISC-V, too.
All of these are hidden deep inside the product. So even if you have heard the name, it may not mean much to you yet. This article first explains what an "instruction set" is. Then it looks at what is new about RISC-V.
An instruction set is a contract between software and the CPU
A CPU is the part that runs simple instructions one at a time, such as "add," "compare" or "read from memory." The instructions are not written in letters. They are patterns of 0s and 1s, called machine code. For details, see "What Is a CPU?"
Which instructions exist, and which pattern of 0s and 1s stands for each one? This set of rules is called an instruction set. Its formal name is instruction set architecture, or ISA for short. The instruction set also fixes other details. Examples are the number of small storage slots inside the CPU and the length of each instruction.
The key point is that an instruction set only defines "what to do." It does not define "which circuit does it." Each company that builds a CPU is free to design the circuit its own way. So the same machine-code program runs on any CPU that follows the same instruction set. That can be a tiny microcontroller or a high-end CPU. A later section covers the fine print.
Three major instruction sets, and the right to use them
Today the best-known instruction sets are x86, Arm and RISC-V. They differ in technical ways, too. But the biggest difference is "who can build CPUs, and on what terms."
x86 is the instruction set that grew out of the 8086, which Intel announced in 1978. It is used in many Windows PCs and servers. x86 CPUs are made mainly by two companies, Intel and AMD. Other companies cannot freely build and sell x86 CPUs.
Arm is an instruction set owned by Arm, a UK company. Arm lets other companies use its instruction set, and these fees are its main income. According to Arm's annual report, there are two main ways to do this. One is to license a CPU design that Arm itself has made. The other is to license only the instruction set, so the customer designs its own CPU. Either way, the customer pays a fee for the contract (a license fee). It also pays a fee for each chip it ships (a royalty).
For RISC-V, the specification is published so anyone can read it for free. You can design and sell a CPU that follows RISC-V without paying license fees or royalties. Nothing is owed to the group that manages the specification. A standard published for anyone to use like this is called an "open standard." However, the "RISC-V" name and logo are trademarks of that group. Using them on products follows separate rules.
| x86 | Arm | RISC-V | |
|---|---|---|---|
| Who sets the specification | Intel and AMD | Arm | RISC-V International (members discuss it) |
| Who can build CPUs | Mainly Intel and AMD | Companies with an Arm contract | Anyone |
| Fees for the instruction set | Not open to other companies | License fee and royalties | None |
This table is a rough summary of the business models. For a technical comparison, see the table in "ARM vs RISC-V vs x86."
Where did RISC-V come from?
RISC-V started in May 2010 at the University of California, Berkeley. It was part of a research project begun by Professor Krste Asanović and graduate students Yunsup Lee and Andrew Waterman. In research and teaching, people often want to change a CPU's inner workings freely and publish the results. But existing instruction sets could not be freely changed, and changed versions could not be shared.
The "RISC" in the name is a design approach. It keeps the number of instruction types small and makes each instruction simple and uniform. Simple instructions make circuits easier to build and easier to run fast. The opposite approach gives one instruction a lot of work to do. It is called CISC, and x86 belongs to this group. For the differences, see the table in "RISC vs CISC."
In a RISC instruction set, only special instructions read from or write to memory. Calculations happen between small storage slots inside the CPU, called registers. This approach is called a load-store architecture, and both Arm and RISC-V use it. Because each instruction does a simple, uniform job, the circuit can easily process instructions in sequence.
The "V" is the Roman numeral five. Berkeley has run RISC research over many generations, starting with RISC-I, announced in 1981. According to the specification, RISC-V is the fifth major design in that line.
In 2014, Professor Asanović and Professor David Patterson published a report arguing that "instruction sets should be free." In 2015, the RISC-V Foundation was formed to develop the specification, and many companies joined. In March 2020, this group was incorporated in Switzerland and took its current name, RISC-V International. It is a non-profit group, and its members decide the specification through discussion.
A small base, plus extensions you choose
A standout feature of RISC-V is that you combine parts of the instruction set like building blocks. The foundation is a small "base instruction set." It has only integer math, memory reads and writes, and branches. A branch picks which instruction runs next, based on a condition. There is RV32I, which handles 32-bit numbers, and RV64I, which handles 64-bit numbers. By the specification's count, RV32I has only 40 instructions.
On top of this base, you add only the features you need, as "extensions." Each extension is named with a single letter. The main ones are listed below.
- M: Integer multiply and divide (these are not in the base instruction set)
- A: Instructions that read and write memory without being interrupted midway. A core is a circuit that runs instructions. These instructions keep shared data intact when several cores use it.
- F and D: Math on numbers with fractions. F is standard precision, and D is double that precision.
- C: Lets common instructions be written in a short 16-bit form instead of the usual 32 bits
- V: Does the same calculation on lots of data at once (the vector extension, ratified in 2021)
Shortened instructions like those in C are called compressed instructions. According to the specification, 50–60% of instructions can usually be replaced with the short form. As a result, programs get 25–30% smaller. On a microcontroller with little memory, that difference matters a lot.
A CPU's name tells you which extensions it has. For example, Espressif's ESP32-C3, covered below, is "RV32IMC." That means the 32-bit base plus M (multiply and divide) and C (short instructions). The specification also leaves room for each company to add its own instructions. A company can add instructions tuned for a specific job, such as AI math.
Where is it used?
RISC-V first spread through small CPUs that handle one fixed job inside a product. These CPUs are hidden from view, and one machine often holds several of them. Because there are so many, having no per-chip royalty is a big advantage.
- Storage control: In 2017, Western Digital announced it would move the cores that control its products to RISC-V. At the time, the company used more than 1 billion cores a year. In December 2018, it announced it would release "SweRV," its own RISC-V core design for SSDs and other products.
- Microcontrollers: In November 2020, Espressif announced the ESP32-C3 microcontroller. It has Wi-Fi and Bluetooth built in. Its CPU is a 32-bit RISC-V that runs at up to 160 MHz.
- Control inside GPUs: A GPU contains small CPUs that manage the whole chip. Since the mid-2010s, NVIDIA has been switching these from its own in-house design to RISC-V. According to a talk at a 2024 RISC-V conference, one chip holds about 10 to 40 RISC-V cores.
Many chips today are an SoC: one chip that combines a CPU with other circuits, such as those for computing or communication. Inside such chips, RISC-V is already used in huge numbers as a "supporting" CPU.
As the "main" CPU in PCs and smartphones, though, it is just getting started. In February 2025, a RISC-V mainboard for the Framework Laptop 13 went on sale. But the maker itself says it is "for developers, not general consumers."
An open instruction set does not mean an open CPU design
Here it helps to separate two things that are easy to mix up. The instruction set is the contract for what to do. A CPU design says which circuit does it. In "What Is a CPU?", a full set of circuits that runs instructions was called a "core." In the industry, the design of that circuit is also called a "core." What RISC-V makes public is the instruction set. Each core design belongs to the company that made it.
In fact, most RISC-V cores are closed, commercial products. Take SiFive, a company founded in 2015 by the three people at Berkeley who started RISC-V. It licenses its core designs to other companies for a fee. This resembles Arm's model, but there is no fee for the instruction set itself. According to press reports, the cores inside NVIDIA's GPUs are also NVIDIA's own designs.
On the other hand, some cores publish their full design as well. Examples are Ibex, now developed by the UK non-profit lowRISC, and CVA6, managed by the OpenHW group. As with "open source" in the software world, anyone can read, use and improve them. So "RISC-V chips" include both closed and open designs.
The biggest challenge: building up the software
A CPU is useless without software written for its instruction set. It needs an operating system, compilers, common code collections (libraries) and apps. x86 and Arm have decades of software behind them. They also have decades of tuning to make that software run fast. The whole network of this software, the tools, and the people and companies behind them is called an "ecosystem."
Software for RISC-V is slowly catching up. For example, Debian is one of the major Linux-based operating system distributions. Its August 2025 release added 64-bit RISC-V as an officially supported platform for the first time. Still, not every app that many people use on PCs and phones is available yet.
Being free to choose extensions is also a weak point for software. If each CPU has different extensions, it is hard to write software that "runs on any RISC-V CPU." So RISC-V International defines, for each use, a set of extensions that a CPU must have at minimum. In October 2024, it ratified one such set, called "RVA23." It targets 64-bit CPUs that run full operating systems.
Common misconceptions
Myth: RISC-V is free, so RISC-V chips cost nothing to make
In fact, the only free part is the right to use the instruction set, the "contract." Designing a CPU circuit that follows it is still very expensive. So are testing it and having a factory make it. If you license a core design from another company, you pay for that too. The accurate version is this: with no fee for the instruction set, costs come down and design freedom goes up.
Myth: RISC is slow because its instructions are simple (or: RISC is fast because it is RISC)
In fact, a CPU's speed depends far more on its circuit design, cache size and manufacturing technology than on RISC vs. CISC. A 2013 study at the University of Wisconsin–Madison measured real Arm and x86 CPUs. It concluded that differences in performance and power come from design differences, not the type of instruction set. Modern x86 CPUs split complex instructions into simple internal steps before running them. You cannot say a CPU is fast or slow "because it is RISC-V." You need to compare individual products.
Myth: Any RISC-V CPU runs the same software
In fact, software that uses only the base instructions will run. But software that uses an extension runs only on CPUs that have that extension. For example, software that uses V (vector) will not run on a small microcontroller without V. There are also differences in operating systems and surrounding parts. Sets of rules like RVA23, from the previous section, exist to reduce this problem.
By the numbers
| Item | Figure | Notes |
|---|---|---|
| Start of RISC-V | May 2010 | At Berkeley. RISC research dates back to RISC-I in 1981 |
| Instructions in RV32I (the base) | 40 | By the specification's count. 32 registers |
| Program size reduction with the C extension | 25–30% smaller | Specification's estimate |
| Scale of Western Digital's switch | Over 1 billion a year | As of the 2017 announcement |
| RISC-V cores per NVIDIA chip | About 10–40 | 2024 talk |
| Managing group incorporated in Switzerland | March 2020 | RISC-V International |
The number 40 shows how small the "base" of the instruction set is. x86 has kept adding instructions for decades. So, depending on how you count, it has far more instruction types than this. RISC-V was first created for university research and teaching. Its small base also makes it a good teaching tool for students designing a CPU from scratch.
Learn more
- See the differences in a table: ARM vs RISC-V vs x86, RISC vs CISC
- Terms to learn next: compressed instruction, load-store architecture, atomic instruction (the instructions in the A extension), IEEE 754 (the number format the F and D extensions follow)
- How microcontrollers, a common home for RISC-V, work: "What Is a Microcontroller?"
- How a program becomes machine code for a specific instruction set: "How Compilers Work"
- How companies design their own chips and have others make them: "What Is a Semiconductor Foundry?"