ISA & Assembly

In RISC-V, what can happen when the address of a 4-byte lw is not a multiple of 4 (misaligned)?

  1. AThe address is silently rounded to the next multiple of 4 and always read correctly at full speed
  2. BDepending on the implementation, it may raise an exception or be handled in hardware or software, possibly very slowly
  3. CThe low two address bits are simply ignored without error
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Answer: B. Depending on the implementation, it may raise an exception or be handled in hardware or software, possibly very slowly

A 4-byte item at an address that is a multiple of 4 can be read in one memory access. Crossing a boundary needs two accesses, so RISC-V lets each implementation either handle misaligned accesses in hardware or trap and leave them to software, which can be orders of magnitude slower. This is why compilers insert padding between struct members to keep them aligned.

  • A. The address is never silently changed.
  • B. Correct. The ISA allows implementations either way.
  • C. Ignoring them would read the wrong location.
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More ISA & Assembly questions

  1. The RISC-V instruction "slli t0, a0, 3" makes t0 how many times the value of a0 (ignoring overflow)?
  2. a0 holds the start address of an int (4-byte) array a, and a1 holds an index i. What does the code above load into a2?
  3. Which statement is correct about designs like x86, where an arithmetic instruction such as "add eax, [rbx]" can use a memory value directly?
  4. How do today's high-performance x86 CPUs execute complex instructions internally?
  5. What instructions does the RISC-V M extension add to the base integer instruction set?