ISA & Assembly

How do today's high-performance x86 CPUs execute complex instructions internally?

  1. AThey execute every instruction one at a time in a software emulator
  2. BThey decode instructions into simple, RISC-like micro-operations and execute those in a pipeline
  3. CThey cannot run complex instructions, so the OS stops them with an error
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Answer: B. They decode instructions into simple, RISC-like micro-operations and execute those in a pipeline

x86 CPUs break variable-length, complex instructions into simple operations called micro-operations (μops) in the front-end decoder, and the back end executes them out of order. Some CPUs keep a μop cache so decoded μops can be reused without decoding again. This lets them keep compatibility with old software while using the same fast execution techniques as RISC designs.

  • A. They are not emulated in software.
  • B. Correct. CISC outside, close to RISC inside.
  • C. Complex instructions do run.
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More ISA & Assembly questions

  1. What instructions does the RISC-V M extension add to the base integer instruction set?
  2. What is the main purpose of the RISC-V C extension (compressed instructions)?
  3. When C's "a * b" (multiplying two ints) is compiled for an RV32I CPU without the M extension, what generally happens?
  4. What is true of the branch delay slot found in older ISAs such as MIPS (the rule that the one instruction right after a branch always executes, taken or not)?
  5. On 64-bit RV64I, how does lw place the 32-bit value it loads into a 64-bit register?