ISA & Assembly

In RISC-V instructions, each register field (rd, rs1, rs2) is 5 bits wide. Why?

  1. ABecause the registers are 5 bits wide
  2. BBecause one instruction can use up to five registers
  3. CThere are 32 integer registers, and 2^5 = 32 values can name each of them
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Answer: C. There are 32 integer registers, and 2^5 = 32 values can name each of them

An R-type instruction consists, from the top, of funct7 (7 bits), rs2 (5), rs1 (5), funct3 (3), rd (5) and opcode (7), 32 bits in total. With 32 registers, a register number fits in 5 bits. Going to 64 registers would need 6 bits per field, 3 extra bits for three fields, leaving fewer bits for immediates and opcodes. The number of registers is tied to the instruction format.

  • A. Registers are 32 or 64 bits wide.
  • B. Base instructions use at most three registers: rd, rs1 and rs2.
  • C. Correct. Five bits encode 0 to 31.
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More ISA & Assembly questions

  1. The immediate of RISC-V addi is a 12-bit signed integer. What range can it represent?
  2. In RISC-V, what is the usual way to put a 32-bit constant that does not fit in a 12-bit immediate (e.g. 0x12345678) into a register?
  3. To build the constant 0x12345FFF in RISC-V with lui and addi, which pair is correct?
  4. What does the RISC-V auipc instruction (add upper immediate to PC) do?
  5. On RISC-V RV32I, what 32-bit value is in t0 after "addi t0, zero, -1"?