ISA & Assembly
What is true of the branch delay slot found in older ISAs such as MIPS (the rule that the one instruction right after a branch always executes, taken or not)?
- AIt makes branch prediction 100% accurate and is essential in today's CPUs
- BRISC-V adopts it too, so a nop must follow every branch
- CIt exposed a quirk of the pipelines of its time in the ISA and later became a burden for CPU designs
Show answer and explanation
Answer: C. It exposed a quirk of the pipelines of its time in the ISA and later became a burden for CPU designs
In a simple five-stage pipeline, the next instruction has already been fetched by the time a branch resolves, so the delay slot made it always execute to avoid waste. In later CPUs with deep pipelines, branch prediction and multiple issue, the benefit vanished and only the burden of special handling for compatibility remained. RISC-V avoids it so as not to bake implementation-dependent rules into the ISA.
- A. It is not branch prediction and is unnecessary today.
- B. RISC-V does not have branch delay slots.
- C. Correct. It froze a microarchitectural detail into the ISA.