ISA & Assembly

How do RISC-V and x86 differ in their mechanism for conditional branches?

  1. ARISC-V branches on flags; x86 branches compare two registers directly
  2. BNeither has conditional branches; both choose targets with a lookup table
  3. CIn RISC-V the branch compares two registers directly; in x86 the branch tests flags set by a compare instruction
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Answer: C. In RISC-V the branch compares two registers directly; in x86 the branch tests flags set by a compare instruction

In x86, "cmp eax, ebx" compares and sets flags (condition codes) such as zero and carry, and the following "je" or "jl" branches on those flags. RISC-V has no flags; the branch itself compares two registers, as in "beq a0, a1, L" or "blt a0, a1, L". With no implicit state like flags, dependences are easier to track when instructions are reordered or executed in parallel.

  • A. It is the other way around.
  • B. Both have conditional branch instructions.
  • C. Correct. RISC-V compares and branches in one instruction.
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More ISA & Assembly questions

  1. What does the RISC-V instruction "slt t0, a0, a1" do?
  2. When the RISC-V code above finishes, what is the value in t0?
  3. RISC-V conditional branches (B-type) encode the distance as a 13-bit signed byte offset whose lowest bit is always 0 and not stored. Roughly what range can a branch reach directly?
  4. What does the RISC-V instruction "jal ra, func" do?
  5. Which real instruction executes the RISC-V pseudo-instruction "ret"?