Hardware Security: Advanced Topics and Trends

Which correctly describes the capabilities used in the instruction-set extension called CHERI?

  1. APointer values are encrypted with a key inside the CPU before being placed in memory and decrypted on each use, so that other programs and the OS cannot read pointer values
  2. BThe CPU checks the digital signature attached to the program's executable file each time it executes one instruction and refuses to execute unsigned instructions
  3. CA pointer carries the range it may access and its permissions, and a 1-bit tag that software cannot write distinguishes in memory whether it was created legitimately
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Answer: C. A pointer carries the range it may access and its permissions, and a 1-bit tag that software cannot write distinguishes in memory whether it was created legitimately

CHERI replaces address-only pointers with capabilities that bundle the address, the upper and lower bounds of the range it may point to, and permissions such as read, write and execute (for 64-bit addresses they are compressed into 128 bits, with a separate 1-bit tag). The CPU checks the bounds and permissions on every access, so memory-safety errors such as reading or writing outside an array can be stopped in hardware. The tag is set only when a capability is created with the proper instructions and is cleared when it is overwritten as ordinary data, so pointers cannot be forged. The University of Cambridge and others have led the research, and in the early 2020s Arm made Morello, a prototype processor and evaluation board based on it, available to researchers.

  • A. It does not hide pointers; it gives them a usable range and permissions and stops out-of-bounds accesses.
  • B. Checking the signature of an executable is done by secure boot and similar mechanisms and is separate from capabilities.
  • C. Correct. Bounds, permissions and the tag prevent out-of-bounds accesses and pointer forgery.
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More Hardware Security: Advanced Topics and Trends questions

  1. In Arm MTE (Memory Tagging Extension), a 4-bit tag is attached to every 16 bytes of memory and a 4-bit tag is also placed in the upper bits of the pointer, and the CPU checks on every access whether the two match. Consider the error of accessing a freed region through an old pointer to it. If the new tag given when the region is reallocated is chosen uniformly at random from the 16 possibilities, what is the probability that the tags match by chance and the error is missed?
  2. Which correctly describes the mechanism of Arm pointer authentication (PAC)?
  3. Which correctly describes the hardware shadow stack adopted in Intel CET (Control-flow Enforcement Technology) and elsewhere?
  4. Regarding hardware features that support control-flow integrity, which correctly pairs what protects returns from functions with what protects indirect calls and jumps such as those through function pointers?
  5. Which correctly explains why Rowhammer is said to become more likely as DRAM is scaled down?