Hardware Security: Advanced Topics and Trends

Suppose a firmware signature check is skipped by a single fault injection attempt with a probability of 1/1,000. The same check is now done in two places, so that the attack succeeds only if both are skipped. If one attempt can target both places at once and each is skipped independently with probability 1/1,000, what is the expected number of attempts until the attack succeeds?

  1. A1,000
  2. B2,000
  3. C1,000,000
Show answer and explanation

Answer: C. 1,000,000

The probability that both are skipped in one attempt is (1/1,000) × (1/1,000) = 1/1,000,000. When attempts with success probability p are repeated, the expected number until the first success is 1/p, so it is 1,000,000 (one million), 1,000 times the 1,000 needed with a single check. However, this calculation assumes that the two faults occur independently. Designs in which one malfunction skips both (such as writing the same comparison twice in a row) gain little, so measures such as staggering the timing of the checks, comparing inverted values and inserting random delays are added.

  • A. This is the expected value with a single check.
  • B. This treats the second place as an addition. The probability that two independent events both occur is a product.
  • C. Correct. 1 ÷ (1/1,000)² = 1,000,000.
Practice this topic Back to topic

Books on Hardware Security: Advanced Topics and Trends Ad

As an Amazon Associate I earn from qualifying purchases.

More Hardware Security: Advanced Topics and Trends questions

  1. Among the TEEs used in confidential computing, which correctly describes the difference between VM-based TEEs that protect a whole virtual machine (such as AMD SEV-SNP and Intel TDX) and enclave-based TEEs that protect part of an application (such as Intel SGX)?
  2. Why was encrypting virtual machine memory alone considered insufficient in VM-based TEEs, so that mechanisms protecting memory integrity were added, as in AMD SEV-SNP?
  3. Consider a circuit that adds tamper detection and replay protection to memory encryption. For every 64-byte cache line, an 8-byte MAC (a code for detecting tampering) and an 8-byte counter that increases on every write are stored in main memory. Ignoring the tree that protects the counters, what is the extra storage needed as a proportion of the amount of data protected?
  4. In confidential computing, a user's verification server (the verifier) checks the attestation report received from a VM-based TEE before handing over the key that decrypts the data. Which is the most appropriate set of things for the verifier to check?
  5. As of the mid-2020s, some data-center GPUs provide features that let them be used for confidential computing together with a CPU TEE. Which correctly describes the idea of this mechanism?