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Hardware Security: Advanced Topics and Trends

The lifecycle state of a security chip is managed in stages such as test, production and failure analysis of returned parts (RMA). Which is an appropriate way to handle moving from the production state to the RMA state for failure analysis?

  1. ATo make analysis easier, open all test and debug functions while keeping the keys and user data used in production
  2. BErase or disable secrets such as the keys used in production before opening the analysis functions, and make it impossible to return to the production state
  3. CReturn a chip that has been moved to the RMA state to the production state as soon as analysis is finished, so that it can be shipped again as new
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Answer: B. Erase or disable secrets such as the keys used in production before opening the analysis functions, and make it impossible to return to the production state

Failure analysis requires opening powerful test and debug functions, but doing so as is risks the keys and user data used in production being read out. So the procedure for moving to the RMA state erases the production secrets or cuts off the paths that use them, and the analysis functions become available only afterwards. If the state transitions are recorded in OTP or eFuses so that they are one-way and the chip cannot go back from RMA to production, a chip opened for analysis never returns to circulation. Published root-of-trust designs such as OpenTitan also define this kind of lifecycle state management.

  • A. Opening debug functions while secrets remain risks keys and user data being read out.
  • B. Correct. The analysis functions are opened after the secrets are erased, and there is no way back.
  • C. Returning a chip whose functions were opened for analysis to production means its security cannot be guaranteed.
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  1. Which correctly pairs the reason why scan chains for scan testing can become an attack path in a chip that performs cryptographic processing with a countermeasure?
  2. Which correctly explains the main reason a chip malfunctions under a voltage glitch that lowers the supply voltage for an instant?
  3. Among fault injection attacks, which correctly pairs the characteristics of methods using a laser and methods using electromagnetic pulses?
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  5. Suppose a firmware signature check is skipped by a single fault injection attempt with a probability of 1/1,000. The same check is now done in two places, so that the attack succeeds only if both are skipped. If one attempt can target both places at once and each is skipped independently with probability 1/1,000, what is the expected number of attempts until the attack succeeds?