Which correctly pairs techniques that protect semiconductor designs with the untrusted party each mainly assumes?

Answer: B. Split manufacturing: the foundry that manufactures it; IC camouflaging: those who read the circuit from chip images; logic locking: the foundry or those holding chips without the key

In split manufacturing, the transistors and lower wiring layers (FEOL) are made at an external leading-edge foundry and the upper wiring layers at a trusted facility, so the external foundry cannot see the full connectivity of the circuit. IC camouflaging uses cells that look the same but have different functions, or fake contacts that only appear connected, to make reverse engineering that reads the circuit from images of a delayered chip harder, but it does not work against a foundry that holds the design data. Logic locking inserts gates whose function changes with a key and keeps the circuit from working correctly until the correct key is written after manufacturing, aiming to stop the foundry from stealing the design or producing extra chips. Since an attack was demonstrated in 2015 in which an adversary with a working chip compares inputs and outputs and narrows down the key with a SAT solver, research on schemes that resist it has continued.

• A. The pairing is wrong. Split manufacturing targets the foundry and camouflaging targets those who reverse-engineer the chip.
• B. Correct. For each technique, the untrusted party sits at a different point in the design and manufacturing flow.
• C. All of them assume adversaries at the hardware design, manufacturing or distribution stages.