Hardware Security: Advanced Topics and Trends
Which correctly pairs the reason why scan chains for scan testing can become an attack path in a chip that performs cryptographic processing with a countermeasure?
- ASwitching to test mode in the middle of processing can let values of key-related registers be read out. Secrets are cleared on the mode switch, and after shipment scan is disabled or requires authentication
- BScan chains consume a lot of power during operation, which disturbs the power waveform and makes power analysis impossible. Therefore scan chains are connected to be as long as possible
- CScan chains only add wiring inside the chip and cannot be used to read data inside the chip out. Therefore no particular countermeasure is needed
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Answer: A. Switching to test mode in the middle of processing can let values of key-related registers be read out. Secrets are cleared on the mode switch, and after shipment scan is disabled or requires authentication
Scan design connects the flip-flops inside a chip so that the internal state can be set and read from outside. Research has shown that if intermediate states of a cryptographic circuit can be read out through scan, the key can be inferred by comparing intermediate values while varying the inputs. Countermeasures are therefore combined: resetting key registers and the like when switching to test mode, removing key registers from the chain, scrambling the scan output, and disabling scan with eFuses at shipment or allowing it only after authentication. Ease of testing and protection of secrets conflict, so both are considered early in the design.
- A. Correct. The read-out path meant for testing is kept from being used to read secrets.
- B. Scan chains are not a mechanism for preventing power analysis, and making them longer is no countermeasure.
- C. Scan chains are precisely the mechanism for reading out the internal state.
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