Hardware Security: Advanced Topics and Trends

As of the mid-2020s, some data-center GPUs provide features that let them be used for confidential computing together with a CPU TEE. Which correctly describes the idea of this mechanism?

  1. ABecause the GPU is outside the CPU TEE, data to be computed on the GPU are handed to the hypervisor unencrypted, and the hypervisor is trusted to have them computed
  2. BThe GPU also proves its state by attestation, and data exchanged between the CPU TEE and the GPU are encrypted and protected against tampering before being sent
  3. CThe data in GPU memory are re-encrypted with the CPU TEE's key on every computation, and the GPU proceeds with the computation on the ciphertext without decrypting it
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Answer: B. The GPU also proves its state by attestation, and data exchanged between the CPU TEE and the GPU are encrypted and protected against tampering before being sent

AI training and inference process models and data on GPUs, so the CPU TEE alone cannot fully protect data being processed. The GPU's firmware and configuration are therefore proven by attestation, the verifier checks them before handing over keys, and the GPU is treated as part of the TEE. Data between the CPU and the GPU pass through memory managed by the hypervisor and through the PCIe path, so they are encrypted and protected against tampering with a key shared by the two before being sent. Inside the GPU the computation runs on decrypted data, and access to the GPU's internal memory from the host side is restricted.

  • A. Handing data over unencrypted would let the hypervisor read them, which is not confidential computing.
  • B. Correct. After proving the GPU, the path is protected and the range of trust is extended.
  • C. A GPU cannot compute on ciphertext as is (this is not homomorphic encryption). Inside, it computes on decrypted data.
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More Hardware Security: Advanced Topics and Trends questions

  1. Which correctly describes the realm introduced in Arm CCA (Confidential Compute Architecture)?
  2. Which correctly describes the capabilities used in the instruction-set extension called CHERI?
  3. In Arm MTE (Memory Tagging Extension), a 4-bit tag is attached to every 16 bytes of memory and a 4-bit tag is also placed in the upper bits of the pointer, and the CPU checks on every access whether the two match. Consider the error of accessing a freed region through an old pointer to it. If the new tag given when the region is reallocated is chosen uniformly at random from the 16 possibilities, what is the probability that the tags match by chance and the error is missed?
  4. Which correctly describes the mechanism of Arm pointer authentication (PAC)?
  5. Which correctly describes the hardware shadow stack adopted in Intel CET (Control-flow Enforcement Technology) and elsewhere?