Hardware Security: Advanced Topics and Trends

Which correctly describes the hardware shadow stack adopted in Intel CET (Control-flow Enforcement Technology) and elsewhere?

  1. AThe contents of the stack are saved to non-volatile memory at regular intervals, and when a program terminates abnormally, execution resumes from them
  2. BLocal variables of functions are placed in fast memory separate from the normal stack, reducing cache misses and speeding up function calls
  3. COn a call, a copy of the return address is also placed on a separate stack that ordinary writes cannot change, and the two are compared on return
Show answer and explanation

Answer: C. On a call, a copy of the return address is also placed on a separate stack that ordinary writes cannot change, and the two are compared on return

If a return address is overwritten by a stack buffer overflow or similar, execution jumps to a place chosen by the attacker when the function returns. With a shadow stack, the call instruction pushes the return address onto both the normal stack and the shadow stack, and the ret instruction compares the two. Shadow-stack pages are a special page type that ordinary store instructions cannot write, so an attacker who overwrote the normal stack cannot change the copy, and a mismatch raises an exception that stops execution.

  • A. It is not a mechanism for recovering from abnormal termination.
  • B. It is not a mechanism for moving local variables to gain speed but one for protecting return addresses.
  • C. Correct. Tampering with the return address is detected just before returning.
Practice this topic Back to topic

Books on Hardware Security: Advanced Topics and Trends Ad

As an Amazon Associate I earn from qualifying purchases.

More Hardware Security: Advanced Topics and Trends questions

  1. Regarding hardware features that support control-flow integrity, which correctly pairs what protects returns from functions with what protects indirect calls and jumps such as those through function pointers?
  2. Which correctly explains why Rowhammer is said to become more likely as DRAM is scaled down?
  3. Which correctly explains why Rowhammer protection by in-DRAM TRR (target row refresh) has been bypassed in research?
  4. What is wrong with the idea that "if ECC memory is used, there is no need to worry about Rowhammer"?
  5. Which correctly describes the idea of PRAC (per-row activation counting), added to the DDR5 standard updated in 2024 (JESD79-5C)?