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Hardware Security: Advanced Topics and Trends

Which correctly explains the main reason a chip malfunctions under a voltage glitch that lowers the supply voltage for an instant?

  1. AAt the instant the voltage drops, all data in the chip's registers and memory are erased to 0 and the chip returns to its state right after power-on
  2. BWhen the voltage drops, the frequency of the chip's internal clock oscillator automatically rises and instruction execution speeds up accordingly
  3. CLower voltage makes transistors slower, so signals do not reach flip-flops before the next clock edge and wrong values are captured
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Answer: C. Lower voltage makes transistors slower, so signals do not reach flip-flops before the next clock edge and wrong values are captured

When the supply voltage drops, transistors can drive less current and gate delays increase. When the timing condition verified in design, that signals arrive within the clock period (setup time), is no longer met, flip-flops capture wrong values. As a result, comparison results may change or branches and instructions may be skipped, so that a signature check may be bypassed. A clock glitch, which inserts a clock period that is too short, likewise breaks the timing condition and causes malfunctions.

  • A. A momentary voltage drop does not erase all data. What is targeted is a malfunction at a specific moment.
  • B. The clock frequency does not rise when the voltage drops. It is the transistors that slow down.
  • C. Correct. Violation of the timing condition is what causes the malfunction.
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More Hardware Security: Advanced Topics and Trends questions

  1. Among fault injection attacks, which correctly pairs the characteristics of methods using a laser and methods using electromagnetic pulses?
  2. A fault injection attempt succeeds with a probability of 0.1% each time, and the results of attempts are independent. Which is closest to the probability of at least one success in 1,000 attempts?
  3. Suppose a firmware signature check is skipped by a single fault injection attempt with a probability of 1/1,000. The same check is now done in two places, so that the attack succeeds only if both are skipped. If one attempt can target both places at once and each is skipped independently with probability 1/1,000, what is the expected number of attempts until the attack succeeds?
  4. Among the TEEs used in confidential computing, which correctly describes the difference between VM-based TEEs that protect a whole virtual machine (such as AMD SEV-SNP and Intel TDX) and enclave-based TEEs that protect part of an application (such as Intel SGX)?
  5. Why was encrypting virtual machine memory alone considered insufficient in VM-based TEEs, so that mechanisms protecting memory integrity were added, as in AMD SEV-SNP?