AD/DA conversion

Why does timing fluctuation (jitter) of the sampling clock become a problem when converting high-frequency signals?

  1. ABecause the clock stops
  2. BBecause errors occur only for DC signals
  3. CBecause the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time
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Answer: C. Because the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time

If the sampling instant shifts by Δt, an error occurs equal to how much the signal changed during that time. The higher the signal frequency, the steeper its slope, so the same jitter produces a larger error and degrades SNR. High-speed, high-resolution ADCs need low-jitter clocks.

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More AD/DA conversion questions

  1. When a microcontroller produces an analog voltage by passing a PWM signal through a low-pass filter, what determines the output voltage?
  2. What does 'MS/s (MSPS)', used to express the conversion speed of an AD converter, mean?
  3. In the transfer characteristic of an AD converter, what is the error called when the output deviates from 0 at zero input?
  4. What is an advantage of using a differential input for an AD converter?
  5. In a delta-sigma AD converter, which digital circuit converts the fast, coarse quantized output into high-resolution data at a lower sampling rate?