Memory Hierarchy

With a cache hit time of 2 cycles, a miss rate of 4% and a miss penalty of 150 cycles, what is the average memory access time in cycles?

  1. A8 cycles
  2. B6 cycles
  3. C152 cycles
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Answer: A. 8 cycles

Average memory access time = hit time + miss rate × miss penalty = 2 + 0.04 × 150 = 2 + 6 = 8 cycles. The hit time applies to every access, and the miss penalty is added only on misses. 6 cycles omits the hit time, counting only the misses. 152 cycles is the time for a single access that misses, not the average. Even a 4% miss rate quadruples the average.

  • A. Correct. 2 + 0.04 × 150 = 8 cycles.
  • B. 6 cycles forgets to add the hit time.
  • C. 152 cycles is the time for one access that misses.
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More Memory Hierarchy questions

  1. A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?
  2. What is the main advantage of a non-blocking cache, which accepts other accesses while a miss is being serviced?
  3. If the L1 miss rate (as a fraction of all accesses) is 4% and the L2 global miss rate (the fraction of all accesses that also miss in L2) is 1%, what is the L2 local miss rate?
  4. With 64 TLB entries and a 4 KB page size, how much memory can be accessed without TLB misses (the TLB reach)?
  5. Which pair correctly states the main advantage and drawback of using large pages (huge pages)?