Memory Hierarchy

How many sets does a 4-way set-associative cache with 32-bit addresses, 32 KB capacity and 64-byte lines have?

  1. A128
  2. B512
  3. C32
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Answer: A. 128

The number of lines is 32 KB ÷ 64 B = 512. A 4-way cache holds four lines per set, so there are 512 ÷ 4 = 128 = 2⁷ sets, giving a 7-bit index and a 32 − 7 − 6 = 19-bit tag. 512 is the line count itself, which equals the set count only when direct-mapped. Raising associativity reduces the number of sets, which adds tag bits and comparators. 32 comes from wrongly dividing the 64-byte line size by the number of ways.

  • A. Correct. 512 lines ÷ 4 ways = 128 sets.
  • B. 512 is the line count, the set count for a direct-mapped cache.
  • C. 32 is not the set count but the result of a wrong division.
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More Memory Hierarchy questions

  1. In a fully associative cache, how many address bits are used for the index (the part that selects a set)?
  2. With an L1 hit time of 1 ns and miss rate of 5%, an L2 hit time of 10 ns and local miss rate of 20%, and main memory access time of 100 ns, what is the average memory access time?
  3. In a direct-mapped cache, elements of two arrays map to the same cache location and evict each other on every alternating access. How is this miss classified?
  4. Which method is effective at reducing the cache misses that occur when a program accesses data for the first time?
  5. Which misses are not reduced even by making a cache fully associative?