What Is CMOS? How nMOS and pMOS Pairs Save Power
CMOS (said "see-moss") is a way of building circuits from pairs of two kinds of transistors, nMOS and pMOS, which turn on for opposite signals. One of each pair is always off. So while the output stays the same, almost no current flows through from the power supply. Thanks to this power saving, most digital chips, such as CPUs and memory, are made with CMOS.
What you'll learn
- Why nMOS and pMOS are "switches that turn on for opposite signals"
- How a NOT gate (inverter) built from the pair works, and why it uses almost no power while it sits idle
- The three times it still uses power (charging and discharging at every switch, leakage, and a brief current straight through)
- Why most digital chips are CMOS, and its history since 1963
- How it relates to the "CMOS" in PC settings and the "CMOS sensor" in cameras
Prerequisites: two ideas. A transistor is a switch flipped by electricity. A computer treats high and low voltage as 1 and 0. Both are explained in "What Is a Transistor?"
In everyday life: billions of switches and a battery
A high-end smartphone chip holds more than 10 billion transistors. Apple's A17 Pro for the 2023 iPhone has about 19 billion. Now imagine that each one let current flow even while doing nothing. The total current would be large. The battery would drain fast, and the chip would get hot.
In reality, that does not happen. One reason is the way CMOS circuits are built. This article looks at why CMOS saves power, and then at where it still uses power.
A note on words: the "inverter" in this article is a tiny circuit that flips 0 and 1. It is not the inverter found in air conditioners and other appliances, which is a device that changes the form of electricity.
How it works 1: two kinds of switch that respond to opposite signals
The transistors in a chip are switches. An electrical signal makes them connect or cut a path for current. The part that receives the signal is called the gate. Whether the gate voltage is high or low decides how the switch is set.
This switch comes in two kinds that act in opposite ways. One is nMOS, which connects when the gate voltage is high, that is, at 1. The other is pMOS, which connects when the voltage is low, that is, at 0.
Send the same signal to both at once, and one connects while the other is always cut off. CMOS is a method that uses this "opposite" behavior. The C stands for "complementary," meaning the two complete each other.
To keep things simple, this article treats both as switches that only connect or disconnect. How they differ inside is covered in the comparison "nMOS vs pMOS."
How it works 2: a pair makes a NOT gate
The simplest CMOS circuit stacks one pMOS above one nMOS. The pMOS on top connects to the positive side of the power supply. The nMOS below connects to the 0 V side. Both gates get the same input, and the output is taken from the point between the two.
When the input is 0, the pMOS on top connects and the nMOS below is cut off. The output connects to the positive supply and becomes 1. When the input is 1, it is the reverse. The output connects to the 0 V side and becomes 0.
The circuit gives out the opposite of its input, so it is called a NOT gate, or an inverter (something that flips). One circuit unit that handles 0 and 1 by a fixed rule is called a logic gate. The kinds and their rules are explained in "What Is a Logic Gate?"
The key point is this. Whether the output is 0 or 1, either the top or the bottom switch is always cut off. So there is no path for current to run straight from the positive supply to the 0 V side.
How it works 3: why it uses almost no power while idle
In the 1970s, before CMOS spread, most computer chips were built from nMOS alone. In this style, a part that always passes current sits between the output and the positive supply. It is either a resistor (a part that holds back current) or a transistor doing the same job.
When the input is 1, the nMOS connects and the output becomes 0. But now current keeps flowing from the positive supply, through the resistor and the nMOS, to the 0 V side. It flows the whole time the output stays at 0, even when nothing is being computed.
A chip holds tens of thousands, even millions, of these gates. In the nMOS-only style, every gate whose output is 0 keeps using power, even while idle. With CMOS, the current while an output is held is almost zero. We say "almost" because of leakage, which comes later.
How it works 4: three times it still uses power
Charging and discharging at every switch
Beyond the output sit the inputs of the next gates and the wiring. These can store a little electric charge. This property is called capacitance. It works the same way as a part built to store charge ("What Is a Capacitor?").
When the output goes from 0 to 1, current flows from the supply through the pMOS into the capacitance of the wiring and the rest. This is called charging. When the output goes from 1 to 0, the stored charge flows out through the nMOS to the 0 V side. This is discharging. Each time current flows, its energy turns into heat, mainly inside the transistors.
So CMOS uses power mainly according to how many times 0 and 1 swap places. A CPU runs in step with a clock-like signal that ticks billions of times a second. In such a CPU, this power is often a large share of the total. This power spent on switching is called dynamic power.
Lowering the voltage works very well
The charge stored in each charging is proportional to the supply voltage. The voltage is also the force that pushes that charge. So halving the voltage cuts the energy per switch to half of a half, which is one quarter.
As a formula, switching power is "the fraction that switches × capacitance × voltage squared × clock ticks per second." In symbols, it is written P = αCV²f. To try it with numbers, use the CMOS power calculator.
Making transistors and wires smaller also shrinks their capacitance. That is one reason each new chip generation spends less energy per switch ("What Does 2nm or 3nm Mean?").
A little leaks even when off
An ideal switch passes no current at all when it is cut off. A real transistor lets a tiny current leak through even when off. The power this leakage keeps using, even while idle, is called static power.
Leakage tends to grow as transistors get smaller, and it also grows as temperature rises. So today's chips use tricks such as cutting the power entirely to parts not in use. The difference between the two kinds of power is laid out in the comparison "Static vs Dynamic Power."
For an instant during a switch, both are on
The input voltage does not jump from 0 to 1 instantly. It rises over a short time. At the in-between voltages, the pMOS and nMOS are both partly connected. For that brief moment, current passes straight from the supply to the 0 V side. This is called short-circuit current. It is usually a smaller part than the power for charging and discharging.
NAND is built the same way
Gates with two or more inputs follow the same idea. The upper path, which makes the output 1, is built from pMOS. The lower path, which makes the output 0, is built from nMOS. And whenever one path connects, the other is always cut off.
For example, a 2-input NAND gate gives out 0 only when both inputs are 1. The lower path has two nMOS in a row (in series). The upper path has two pMOS side by side (in parallel). If both inputs are 1, the lower path connects. If either is 0, the upper path connects. It takes four transistors.
For any input, the upper and lower paths never connect at the same time. So a NAND gate, too, uses almost no power while idle. How gates combine to add numbers is explained in "How Do Computers Use Binary?"
Why are most chips CMOS?
The first reason is the low power we have just seen. Pack billions of transistors on one chip, and even a tiny current in each adds up to a lot of power and heat. CMOS uses almost no current while idle. That made it easier to fit more transistors on one chip (an integrated circuit).
The second is that 0 and 1 are clear. A CMOS output connects firmly to either the positive supply or the 0 V side. In the nMOS-only style, a "tug-of-war" between the resistor above and the nMOS below sets the voltage for 0. So it never reaches exactly 0 V. The bigger the voltage gap between 0 and 1, the harder it is to misread a signal when noise gets onto a wire. (This safety room is called the noise margin.)
The third is that one way of making chips can put many kinds of circuits on a single chip. Circuits that calculate, the small fast memory inside a CPU, and the circuits around DRAM and flash memory can all be made in CMOS. Camera image sensors use the same technology too. They put the pixels that turn light into electricity and the readout circuits on one chip.
On the other hand, other kinds of transistors are also used, for example in parts that handle large amounts of power ("What Is a Power Semiconductor?").
History: from its invention in 1963 to center stage
CMOS was born in 1963 at the research lab of Fairchild, a US company. Frank Wanlass and C. T. Sah presented the circuit that pairs nMOS and pMOS in a conference paper. Wanlass filed a patent in June of that same year. The US patent was granted in December 1967.
But early CMOS had weaknesses in performance, so it did not spread right away. RCA, another US company, put effort into making it, first for space and aviation equipment. In 1968, RCA released the first products of its "CD4000" series of general-purpose logic ICs (according to the Computer History Museum).
In 1970s computer chips, the faster nMOS-only style was the norm, as we saw in How it works 3. CMOS was used mostly where low power mattered most, such as in watches. One example that changed the trend was a fast CMOS memory that Hitachi announced in 1978 (it later became the product HM6147). It matched the speed of Intel's fast nMOS memory, the 2147, with far less current (according to the Semiconductor History Museum of Japan).
| Year | Event |
|---|---|
| 1963 | Wanlass and Sah at Fairchild present CMOS. Wanlass files a patent |
| 1967 | The US patent for CMOS (No. 3,356,858) is granted |
| 1968 | RCA releases the first products of the "CD4000" logic IC series |
| 1978 | Hitachi announces a fast CMOS memory as quick as nMOS memory |
| After that | CMOS spreads to microprocessors, DRAM and more |
The Semiconductor History Museum of Japan says that after Hitachi's memory, CMOS spread to microprocessors, DRAM and more. Today, most chips that do computing are CMOS.
Common misconceptions
Myth: CMOS uses power while its transistors are on
In fact, it uses power mainly when the output "switches." A transistor may be on, but current cannot keep flowing if the rest of its path is blocked by the other transistor, which is off. The myth tends to come from picturing a light, which uses power the whole time it is on. While idle, CMOS uses only the leakage.
Myth: The "CMOS" in a PC's settings screen is about how the CPU is built
In fact, it means a small memory that keeps the BIOS settings and the date and time, even with the power off. (The BIOS is the program that runs first when you turn a PC on.) Older PCs used a low-power CMOS chip for this, such as Motorola's MC146818A. A button-cell battery kept its contents. Today this memory is part of another, larger chip, but the battery is still called the "CMOS battery." "Clear CMOS" is a step that resets these settings to their defaults. It has nothing to do with the CPU's circuits.
Myth: The CMOS in "CMOS sensor" is the name of a part made only for cameras
In fact, it means an image sensor made with the CMOS method. It can use the same kind of manufacturing technology as CPUs. That makes it easy to put the readout and processing circuits on the same chip, and to keep the power low. It is called a CMOS image sensor. The comparison "CMOS vs CCD Image Sensors" sets it against CCD, an older type.
By the numbers
| Number | What it means |
|---|---|
| 2 | Transistors in a CMOS NOT gate (one pMOS and one nMOS) |
| 4 | Transistors in a CMOS 2-input NAND gate |
| 1/4 | Energy per switch when the supply voltage is halved |
| 20 µA max | Supply current of the CMOS IC 74HC00 (four NAND gates), with the inputs held at the supply voltage or 0 V and nothing connected to the outputs (6 V supply, up to 85 °C; TI datasheet) |
| About 15 mA and about 110 mA | Current of Hitachi's 1978 CMOS memory, and of Intel's nMOS memory "2147" of the same speed (values from the Semiconductor History Museum of Japan) |
A µA (microampere) is one millionth of an ampere, and a mA (milliampere) is one thousandth. The 74HC00's 20 µA is the upper limit for all four gates together. Hitachi's memory drew about one seventh of the current (this site's calculation).
Learn more
- See it in a figure: the figure "CMOS inverter" shows how the transistors of a NOT gate are arranged.
- Compare in a table: "CMOS vs TTL" (two styles of logic IC), and "Clock Gating vs Power Gating" (ways to pause parts of a chip to save power)
- Try it yourself: the logic circuit simulator (place NOT and NAND gates and run them)
- Terms for the next step: threshold voltage (the voltage at which a switch turns on), and DVFS (changing the voltage and speed to match the workload)
- A failure to watch for: latch-up (a fault in which a large current keeps flowing through a path that forms by accident inside CMOS)
- Read on: what happens after power turns into heat, in "How Are Chips Cooled?"; and how wiring capacitance sets speed, in "RC Time Constant Explained."