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Clock Gating vs Power Gating: Key Differences Explained

Both are low-power design techniques that reduce the power of unused circuits, but they stop different things. Clock gating stops the clock to registers, eliminating signal switching and reducing dynamic power. Power stays on, so state is retained and operation can resume immediately within one to a few cycles. Power gating cuts a block's power with a switch, eliminating almost all static power from leakage current in addition to dynamic power. The trade-off is that state is lost, so a mechanism to save it is needed, and wake-up takes longer.

AspectClock gatingPower gating
Power reducedDynamic power (switching in the clock network, flip-flops and downstream logic)Both static power (leakage) and dynamic power
What is stoppedThe clock to registersThe power supply to the block
Power supplyStays on. Leakage current keeps flowingPower switches disconnect the block's supply rail
State retentionRetainedLost. Required state is saved in retention flip-flops (retention registers) or memory
Wake-up timeOne to a few cyclesLong. Power is restored while limiting inrush current and the state is restored, typically on the order of µs
Required circuitsICG (a clock-gating cell built from a latch and an AND gate) and logic to generate the enablePower switches (headers or footers), isolation cells, retention flip-flops and a power sequencing controller
GranularityFine. Can be applied to groups of just a few registersCoarse. Applied per block (power domain), such as a CPU core or an IP block
Design and verificationLogic synthesis tools can insert it automatically from enable conditions. STA performs clock-gating checksPower intent is described in UPF or similar formats, and behavior and sequencing when power is cut must also be verified
OverheadSmall. ICG area and delayPower switch area and voltage drop, plus energy to save and restore. Not worthwhile for short idle periods
Typical useIn almost all digital circuits, stopping the registers of inactive functionsShutting down blocks that are unused for long periods. Deep CPU idle states, unused blocks in smartphone SoCs

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Clock gating
Any time a circuit has an inactive period, from a few cycles to long durations. It resumes immediately and retains state, so it is used in almost all digital circuits.
Power gating
When a block is unused for a long time, or when leakage power is a large share (advanced processes or high temperatures). Used when the idle period is long enough to recover the energy spent saving and restoring.
Combined
A common staged approach is to stop the clock first and, if the idle period looks long, save state and cut power as well. It is also combined with DVFS.

FAQ

Why isn't an AND gate alone enough to stop the clock?

Because if the enable signal changes while the clock is 1, a short pulse (glitch) appears on the clock and flip-flops can operate erroneously. An ICG holds the enable in a latch that passes it only while the clock is 0 and then ANDs it with the clock, so no glitch occurs.

Why does power gating take long to wake up?

Because the large capacitance of the powered-down block must be recharged. Turning all the switches on at once causes a large inrush current that drops the supply voltage of other active circuits, so the switches are turned on gradually in sequence. After that, reset and state restoration are also needed.

Why are isolation cells needed?

The outputs of a powered-down block sit at a voltage that is neither 0 nor 1. If active blocks receive them directly, they can malfunction or shoot-through current can flow in their input gates. Isolation cells clamp the signals at the boundary to a fixed value (0 or 1).

Should power be cut even for short idle periods?

Not necessarily. Cutting power uses energy to save and restore state and to recharge capacitance, so unless the block can stay idle longer than the time needed to recover that energy through reduced leakage power (the break-even time), it actually costs more. Use clock gating for short idle periods.

Check your understanding

Which low-power design technique stops the clock to unused circuit blocks to reduce wasted power?

  1. AOverclocking
  2. BClock gating
  3. CScan design
Show answer and explanation

Answer: B. Clock gating

Clock gating stops the clock to idle blocks, eliminating wasted switching in flip-flops and clock wiring to reduce dynamic power. Synthesis tools can insert it automatically for registers whose values do not change under certain conditions. It does not reduce leakage, so it is combined with power gating, which cuts the supply itself. Overclocking raises frequency, and scan design is a test technique.

Which describes power gating?

  1. AStopping only the clock supply to circuit blocks
  2. BSwitching off the power supply to unused circuit blocks, eliminating nearly all their leakage power too
  3. CDoubling the supply voltage to speed up processing
Show answer and explanation

Answer: B. Switching off the power supply to unused circuit blocks, eliminating nearly all their leakage power too

Clock gating stops switching and so cuts dynamic power, but leakage continues as long as power is connected. Power gating turns off a large transistor switch placed between the block and the supply, cutting power itself, so leakage nearly disappears too. Smartphone SoCs aggressively power off idle CPU cores, GPUs and accelerators.

Which correctly pairs a caveat of power-gated blocks with its countermeasure?

  1. AContents always survive power-off, so nothing is needed
  2. BFlip-flop contents are lost, so needed state is saved in retention registers or external memory before power-off
  3. CPower-off doubles the voltage of other blocks
Show answer and explanation

Answer: B. Flip-flop contents are lost, so needed state is saved in retention registers or external memory before power-off

Flip-flops and SRAM in a powered-off block lose their contents, so to resume where it left off, state must be saved before cutting power. Options include retention registers, which pair each flip-flop with a small always-powered storage element, or software writing state out to memory. Saving, restoring and powering up cost time and energy, so for short idle periods it may be better not to cut power.

  1. Which correctly compares clock gating and power gating?
  2. What is the role of the isolation cells placed between a powered-off block and running blocks?
  3. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?

Practice Power Management questions

Key terms explained

Clock gating
A low-power design technique that stops the clock to idle circuit blocks, avoiding wasted switching power.
Power gating
A low-power technique that switches off the supply to unused blocks, eliminating nearly all their leakage. State saving and wake-up time must be considered.
Retention register
A flip-flop that keeps its state in a small always-powered storage element while the block is power-gated, allowing operation to resume where it left off.
Isolation cell
A cell placed at a boundary that passes a fixed value to running logic even when the outputs of a powered-off block are undefined.
Power domain
A region of a chip sharing the same supply voltage and power on/off control, allowing voltage and power to be managed per block.

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