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nMOS vs pMOS: Key Differences Explained

An nMOS is a MOSFET in which electrons flow through the channel, and a pMOS is one in which holes do; all the voltage polarities are reversed. An nMOS turns on when the gate is raised above the source, and a pMOS turns on when the gate is lowered below the source. In silicon, electron mobility is about 2–3 times hole mobility, so for the same dimensions an nMOS can carry more current. In CMOS circuits, the nMOS pulls the output to ground and the pMOS pulls it to the supply, and the pMOS gate is made wider to match the drive strength.

AspectnMOSpMOS
Structuren⁺ source and drain in a p-type substrate or p-wellp⁺ source and drain in an n-well
Channel carriersElectronsHoles
Mobility (silicon inversion layer)High. About 2–3 times that of holesLow
Threshold voltage (enhancement mode, referenced to source)Positive (e.g. +0.3 V)Negative (e.g. −0.3 V)
Turn-on conditionVGS > Vth. Raise the gate above the sourceVGS < Vth (negative). Lower the gate below the source by at least |Vth|
Source connection in CMOSGround sideSupply (VDD) side
Role in CMOSPull-down. Pulls the output to ground. In series in NAND, in parallel in NORPull-up. Pulls the output to the supply. In parallel in NAND, in series in NOR
Value passed well as a switchPasses 0 well. A 1 rises only to about VDD − VthPasses 1 well. A 0 falls only to about |Vth|
Gate width needed for equal driveReference (1×)Typically about 2–3 times that of the nMOS
Strain that boosts mobilityTensile strain (stress liners, Si:C source/drain, etc.)Compressive strain (SiGe source/drain, etc.)
Typical degradationPBTI (a concern with high-k/metal gates)NBTI

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

nMOS
When pulling an output down to ground: CMOS pull-down networks, switches that pass 0, switches on the current-sinking side, etc.
pMOS
When pulling an output up to the supply: CMOS pull-up networks, switches that pass 1, switches placed on the supply side (high-side switches), etc.
Combined
CMOS uses both in pairs, and in steady state one of them is always off, so almost no static current flows. A transmission gate, made of an nMOS and a pMOS in parallel, passes both 0 and 1 well.

FAQ

Why is the pMOS gate made wider than the nMOS in CMOS?

Hole mobility is about 1/2–1/3 of electron mobility, so a pMOS of the same dimensions carries less current. Making the pMOS about 2–3 times as wide as the nMOS equalizes the rise and fall delays and puts the inverter's logic threshold at about half the supply voltage.

Why is the threshold voltage of a pMOS negative?

A pMOS needs a hole inversion layer at the surface of the n-type well, and that requires the gate to be at a lower voltage than the source. To avoid confusion over signs, designers often compare the absolute value |Vth|.

Why aren't logic circuits built from nMOS alone?

In nMOS-only circuits, current keeps flowing through a resistor or load device whenever the output is 1, so static power is large. In CMOS, which combines nMOS and pMOS, one of the two is always off in steady state, so almost none of this current flows.

Is the difference between nMOS and pMOS still 2–3 times in advanced processes?

The gap has narrowed considerably, because pMOS mobility is boosted by compressive strain from SiGe source/drain, and FinFETs use crystal planes for the channel along which holes flow more easily. Even so, cell designs still set dimensions with the drive-strength difference between the two in mind.

Check your understanding

For nMOS and pMOS transistors of the same size, the nMOS generally has a larger drive current. What is the main reason?

  1. AThe nMOS gate oxide is always thicker
  2. BA pMOS has no gate electrode
  3. CThe mobility of electrons in the channel is higher than that of holes
Show answer and explanation

Answer: C. The mobility of electrons in the channel is higher than that of holes

Electrons carry current in an nMOS and holes in a pMOS, and in silicon inversion layers electron mobility is about 2–3 times hole mobility, so an nMOS of the same size drives more current. CMOS balances this by widening the pMOS. In advanced processes, compressive strain from SiGe boosts pMOS mobility, and in FinFETs the fin sidewalls are (110) planes, which favor holes, so the gap has narrowed considerably.

Which correctly compares electron and hole mobility in silicon?

  1. AElectron mobility is higher
  2. BHole mobility is higher
  3. CThey are always equal
Show answer and explanation

Answer: A. Electron mobility is higher

In silicon at room temperature and low doping, electron mobility is about 1400 cm²/V·s and hole mobility about 450 cm²/V·s, so electrons are about three times faster, mainly because holes have a larger effective mass. An nMOS of the same size therefore carries more current, and in CMOS the pMOS is typically made 2–3 times wider than the nMOS to balance drive strength. Advanced processes boost pMOS mobility with compressive strain from SiGe.

Which design makes the logic threshold of a CMOS inverter about half the supply voltage?

  1. ARemove the nMOS
  2. BSet the supply voltage to 0 V
  3. CMake the pMOS gate wider than the nMOS so that their drive strengths are balanced
Show answer and explanation

Answer: C. Make the pMOS gate wider than the nMOS so that their drive strengths are balanced

Hole mobility is lower than electron mobility, so a pMOS of the same size is weaker and the switching threshold shifts toward ground. Making the pMOS 2–3 times wider than the nMOS balances drive strength, putting the threshold near half the supply, equalizing high and low noise margins and matching rise and fall delays. Wider pMOS adds area and input capacitance, so speed-critical designs sometimes use a smaller ratio deliberately.

  1. What is the sign of the threshold voltage (relative to the source) of an enhancement-mode p-channel MOSFET?
  2. Which carriers carry the current in the channel of an n-channel MOSFET?
  3. How are the transistors connected in a CMOS two-input NAND gate?

Practice MOSFET questions

Key terms explained

CMOS
A circuit style that combines nMOS and pMOS transistors in a complementary way. Almost no current flows through it in steady state, so power consumption is low.
Mobility
How easily carriers move when an electric field is applied. In silicon, electron mobility is higher than hole mobility.
Threshold voltage
The gate voltage at which a channel (inversion layer) forms in a MOSFET and current starts to flow. Written as Vth.
Transmission gate
An analog switch made of an nMOS and a pMOS connected in parallel. The nMOS passes 0 well and the pMOS passes 1 well, so both values pass without voltage loss.

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