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Static vs Dynamic Power in CMOS: Key Differences

Power in CMOS circuits divides into dynamic power, used when signals switch, and static power, used continuously even without switching. Dynamic power comes from charging and discharging wire and gate capacitance and is expressed as P = αCV²f. Static power comes from leakage current through off transistors and other paths, and it rises sharply as temperature goes up. As scaling lowered supply voltage and threshold voltage, static power grew to a larger share.

AspectStatic powerDynamic power
Also calledLeakage powerSwitching power
CauseSubthreshold leakage of off transistors, gate leakage, junction leakage, etc.Charging and discharging of load capacitance. Sometimes includes short-circuit current when pMOS and nMOS are on at the same time during switching
Rough equationP = V × Ileak (Ileak: leakage current)P = αCV²f (α: activity factor, C: capacitance, V: supply voltage, f: frequency)
When the circuit is idleConsumed as long as power is onAlmost zero if signals do not switch
Dependence on supply voltageIncreases faster than proportionally to voltage, because leakage current itself also increases due to DIBL and other effectsProportional to the square of the voltage
Dependence on frequencyAlmost noneProportional to frequency
Dependence on temperatureStrong. Increases exponentially with temperature and can also cause thermal runawayWeak
Dependence on threshold voltageStrong. Lowering the threshold increases subthreshold leakage exponentially (roughly 10 times for every 60 to 100 mV decrease at room temperature)No direct dependence. However, a high threshold makes the circuit slower
Reduction techniquesPower gating, high-threshold transistors (multi-Vt), lowering voltage in standby, suppressing gate leakage with high-k/metal gatesClock gating, DVFS, lowering supply voltage, reducing capacitance, reducing activity factor
Change with scalingRose sharply because threshold voltage was lowered along with supply voltage, becoming a non-negligible share. Structures with better gate control such as FinFETs keep it in checkUnder Dennard scaling, shrinking dimensions and voltage by the same ratio kept power density constant. As voltage became hard to lower, rising power density became a problem
When it mattersDevices that spend long periods in standby, chips that run at high temperatureWhen running actively at high frequency

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Reducing static power
Devices that spend long periods in standby, and chips that run at high temperature. Power gating cuts power to unused blocks, and high-threshold transistors are used on paths that do not need speed.
Reducing dynamic power
Processors running actively at high frequency. Clock gating stops unnecessary switching, and DVFS lowers voltage and frequency according to the load.
Combined
Lowering the voltage reduces dynamic power with its square, but the circuit becomes slower and processing takes longer, increasing the leakage energy during that time. So there is a voltage at which the energy per operation is minimized.

FAQ

What happens to dynamic power if the supply voltage is halved?

If other conditions are the same, it falls to 1/4, because it is proportional to the square of the voltage. However, lowering the voltage makes the circuit slower, so it may not run at the same frequency.

Why does static power increase with temperature?

Subthreshold leakage, which flows below the threshold, increases sharply because a higher temperature broadens the energy distribution of carriers and also lowers the threshold voltage. Watch out for the vicious cycle in which more heat raises the temperature further.

Does clock gating reduce static power?

Hardly at all. Stopping the clock eliminates switching and reduces dynamic power, but power stays connected, so leakage current keeps flowing. To reduce leakage as well, use power gating, which cuts the power.

Check your understanding

In the CMOS dynamic power formula P = αCV²f, what does α represent?

  1. AThe number of transistors
  2. BThe fraction of signals switching per clock cycle (the activity factor)
  3. CThe chip temperature
Show answer and explanation

Answer: B. The fraction of signals switching per clock cycle (the activity factor)

Dynamic power is consumed charging and discharging the capacitance of wires and gates. C is the switched capacitance, V the supply voltage, f the clock frequency and α the activity factor, the fraction of signals that switch per clock. Parts whose data does not change, or whose clocks are stopped, do not switch, so reducing α is also an important power-saving lever.

Which describes static (leakage) power in CMOS circuits?

  1. APower that grows in proportion to clock speed
  2. BPower consumed continuously by leakage currents through off transistors and the like, even when signals do not switch
  3. CPower used only when manufacturing the chip
Show answer and explanation

Answer: B. Power consumed continuously by leakage currents through off transistors and the like, even when signals do not switch

Transistors are not perfect switches; even when off, small subthreshold and gate leakage currents flow. Each is tiny, but across billions of transistors they add up to significant power, which grew more prominent as scaling lowered threshold voltages. Static power does not fall when clocks stop, so it is addressed by cutting supply power itself, for example with power gating.

How does leakage power change as chip temperature rises, and what problem can result?

  1. AIt rises steeply (exponentially) with temperature, possibly causing a vicious cycle of more heat and higher temperature (thermal runaway)
  2. BIt falls as temperature rises, so hotter means more efficient
  3. CIt is constant regardless of temperature
Show answer and explanation

Answer: A. It rises steeply (exponentially) with temperature, possibly causing a vicious cycle of more heat and higher temperature (thermal runaway)

Subthreshold leakage rises steeply with temperature because the energy distribution of carriers broadens, and it can increase substantially with roughly every 10°C. More leakage means more heat, higher temperature and still more leakage, a positive feedback loop that can lead to thermal runaway if cooling is insufficient. Temperature sensors therefore monitor the chip and controls such as lowering frequency are applied.

  1. Which correctly compares clock gating and power gating?
  2. In a CMOS circuit, if only the supply voltage is halved with everything else unchanged, what happens to dynamic power consumption?
  3. Which combination lists the main components of leakage current in a MOSFET in the off state?

Practice Power Management questions

Key terms explained

Static power
Power consumed continuously by leakage currents through off transistors even when signals do not switch, also called leakage power. It rises steeply with temperature.
Dynamic power
Power consumed in CMOS circuits charging and discharging capacitance when signals switch, expressed as αCV²f with activity factor α, capacitance C, voltage V and frequency f.
Activity factor
The fraction of a circuit's signals that switch per clock cycle, the α in the dynamic power formula αCV²f. It can be reduced by clock gating and similar.
Power gating
A low-power technique that switches off the supply to unused blocks, eliminating nearly all their leakage. State saving and wake-up time must be considered.
Clock gating
A low-power design technique that stops the clock to idle circuit blocks, avoiding wasted switching power.

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