CMOS vs TTL Logic: Differences Explained
TTL (transistor-transistor logic) builds gates from bipolar transistors and was the standard digital family from the 1960s. CMOS builds gates from complementary MOS transistors and has since replaced it almost everywhere. The big difference is power: a CMOS gate draws almost no current when it is not switching, while a TTL gate draws current all the time. CMOS also tolerates a wide supply range, has larger noise margins and can be packed by the billions on a chip.
| Aspect | TTL | CMOS |
|---|---|---|
| Transistors | Bipolar transistors, with multi-emitter input transistors | Complementary nMOS and pMOS transistors |
| Static power | High: current flows even when idle | Very low: only leakage current |
| Supply voltage | Fixed 5 V (about plus or minus 5 percent) | Wide range, from about 1 V to 15 V depending on the family |
| Logic levels | Low up to about 0.8 V and high from about 2.0 V | About 30 percent and 70 percent of the supply voltage |
| Noise margin | Small (about 0.4 V) | Large (about 30 percent of the supply) |
| Output swing | Does not reach the supply rails fully | Swings fully between ground and the supply |
| Inputs | Draw current; an unconnected input floats high | Draw almost no current, but unused inputs must be tied to a level |
| Speed | Fast in its day (74S, 74F families) | Equal or faster in modern families |
| Integration density | Low, because of its power draw | Very high: the basis of VLSI |
| Typical uses | Legacy systems, education and old equipment | Nearly all modern digital chips, including processors and memories |
Figures are typical orders of magnitude and vary by process generation and product.