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CMOS inverter

CMOS inverter VDD pMOS Out nMOS GND In When the input is 0 pMOS on, nMOS off → output 1 When the input is 1 pMOS off, nMOS on → output 0 One of them is always off, so little current flows from VDD to GND

A CMOS inverter connects a pMOS on the supply side and an nMOS on the GND side in series, with the same input applied to both gates. When the input is 0, the pMOS is on and the nMOS is off, so the output is the supply voltage (1); when the input is 1, the pMOS is off and the nMOS is on, so the output is 0.

In either state one of the transistors is off, so almost no current flows from the supply to GND. This is why CMOS consumes so little power. While the input is switching, however, there is a moment when both transistors conduct at once, and a short-circuit current flows.

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Appears in

  1. Why is the static (steady-state) power consumption of a CMOS inverter small?

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