TDDB vs HCI vs NBTI: Transistor Wear-Out Mechanisms and Testing
TDDB, HCI and NBTI are all wear-out mechanisms that slowly degrade transistors over their service life, but they come from different stresses and have different results. TDDB (time-dependent dielectric breakdown) is the build-up of defects in a gate dielectric under a sustained field until the film finally breaks down. HCI (hot carrier injection) is damage to the interface and dielectric by carriers accelerated in the strong field near the drain while current flows. NBTI (negative bias temperature instability) is the growth in threshold-voltage magnitude of a pMOS whose gate is held negative at high temperature, even with no current flowing. TDDB destroys the transistor; HCI and NBTI make circuits gradually slower.
| Aspect | TDDB (time-dependent dielectric breakdown) | HCI (hot carrier injection) | NBTI (negative bias temperature instability) |
|---|---|---|---|
| Mechanism | A small current through the stressed dielectric creates defects (traps); when the defects connect the two electrodes, the film breaks down | Carriers that gain high energy in the strong field near the drain (hot carriers) create interface states or are injected into and trapped in the dielectric | Negative gate bias and heat break Si–H bonds at the Si/SiO2 interface, creating interface states, and positive charge builds up in the dielectric |
| Field direction | Vertical field across the dielectric | Lateral field along the channel (peaks at the drain end) | Vertical field across the dielectric |
| Stress condition | Whenever a large voltage is across the gate dielectric; no current is needed | While current flows with a high drain voltage; in digital circuits, mainly during switching | While a pMOS gate is negative relative to its source (gate low, source at VDD); no current is needed |
| Devices most affected | Every gate dielectric; it also occurs in the dielectric between interconnect lines (BEOL TDDB) | Tends to be worst in short-channel nMOS; also I/O transistors run at higher voltage | pMOS. The nMOS counterpart under positive gate bias is PBTI, which became important with high-k films |
| What shifts | Gate leakage rises, passes through soft breakdown and ends in hard breakdown (a gate short) | Threshold-voltage shift and lower mobility and drive current. Damage is concentrated at the drain side, so swapping source and drain gives asymmetric characteristics | Threshold-voltage magnitude increases, and drive current and transconductance fall |
| Time dependence and recovery | Sudden failure after some time; time to failure is spread out and analyzed with a Weibull distribution. No recovery | Grows gradually as a power law in time. Almost no recovery | Grows as a power law in time with a small exponent, so much of the change happens early. Partly recovers when the stress is removed |
| Temperature and voltage dependence | Lifetime shortens at higher field and higher temperature | Accelerated mainly by drain voltage (lateral field). Temperature dependence varies with device and conditions, and degradation can be larger at low temperature | Strongly accelerated by gate voltage and temperature; worse at high temperature |
| How it is tested | Constant voltage at elevated voltage and temperature until breakdown; times to failure are analyzed statistically and extrapolated to use conditions with models such as the E model or 1/E model | Stress at a drain voltage above use conditions, measure the time until the threshold-voltage or drive-current shift reaches a set criterion, then extrapolate. Substrate current serves as an indicator of susceptibility | Hold a pMOS gate at negative bias at high temperature and measure the threshold-voltage shift. Because it recovers, measure right after the stress is removed, or without removing it |
| Main countermeasures | Better dielectric quality; choosing supply voltage and film thickness to limit the field | LDD structures or extensions to lower the field at the drain edge, lower supply voltage, oxynitride films | Better interface and dielectric processing; aging-aware timing design and guard bands |
Figures are typical orders of magnitude and vary by process generation and product.