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DIBL vs GIDL vs Punch-Through: Where They Occur, Causes, Id-Vg Signatures and Countermeasures

DIBL, GIDL and punch-through all concern leakage current that flows when a transistor should be off, but they occur in different places and for different reasons. DIBL (drain-induced barrier lowering) happens when the gate is short enough for the drain field to reach the source side and lower the potential barrier between source and channel, so the threshold voltage drops as the drain voltage rises. Punch-through happens when the source and drain depletion regions merge and current flows deep in the substrate, out of the gate's reach; it can be seen as an extreme form of DIBL. GIDL (gate-induced drain leakage) is band-to-band tunneling current driven by the strong field where the gate overlaps the drain, and it depends more on the gate-to-drain voltage than on how short the gate is.

AspectDIBLGIDLPunch-through
Where it occursAt the source end of the channel, near the surface, where the source-channel potential barrier is loweredIn the drain, near the surface where the gate overlaps it (the drain edge)In the substrate below the channel, where the source and drain depletion regions merge
Bias that brings it outOff state or near threshold, with a high drain voltageOff state with a large gate-to-drain voltage (for nMOS, gate at 0 V or negative and drain high)High drain voltage; almost independent of gate voltage
Physical causeThe drain field reaches the source and takes over part of the control of the barrier height from the gate (a two-dimensional electrostatic effect)The strong field bends the bands sharply, and electrons tunnel from the valence band to the conduction band (band-to-band tunneling); in nMOS, electrons go to the drain and holes to the bodyThe drain depletion region joins the source depletion region, the barrier inside the substrate disappears, and carriers flow directly from source to drain
How it shows in Id-VgRaising the drain voltage shifts the subthreshold curve to the left (toward lower gate voltage), seen as a lower threshold voltage and higher off currentAs the gate voltage is pushed below threshold, the drain current first falls and then starts to rise again (an upturn on the low gate-voltage side)The subthreshold slope becomes shallow, and lowering the gate voltage does not reduce the current enough to turn the device off
How it shows in Id-VdCurrent keeps increasing with drain voltage even in saturation (lower output resistance)In the off state, current rises with drain voltage, more strongly at lower gate voltageAbove a certain drain voltage, current rises sharply regardless of gate voltage
Dependence on gate length (Lg)Strong: larger at shorter gate lengthWeak: it occurs at the drain edge and is set mainly by other factors (field strength, drain-edge doping, gate dielectric thickness)Very strong: more likely with short gates and lightly doped substrates
Dependence on voltageThreshold voltage falls roughly in proportion to drain voltage; often quoted in mV/VRises steeply with the gate-to-drain voltage (Vdg)Rises steeply with drain voltage; the gate has almost no control
Main countermeasuresThinner gate dielectric (high-k), shallow extensions, halo (pocket) implants, thin bodies (FD-SOI, FinFET, GAA)A more gradual doping profile at the drain edge (such as an LDD structure), optimized gate-drain overlap, limiting the gate-to-drain voltageHigher substrate doping (punch-through stopper implant), halo (pocket) implants, shallow junctions, retrograde wells, structures without a deep current path (SOI, FinFET, GAA)
Where it mattersShort-gate logic transistors in general: standby leakage and reduced gain in analog circuitsDevices that need extremely low off-state leakage, such as DRAM cell transistors, and circuits that turn transistors off with a negative gate voltageTransistors with gates that are too short, or devices with high drain voltage; it sets the limits on usable gate length and voltage

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

DIBL
A metric for how much the threshold voltage and off current of a short-gate transistor change with drain voltage. Extract the threshold voltage at a low and a high drain voltage and divide the difference by the difference in drain voltage.
GIDL
Suspect it when driving the gate harder into the off state (a negative gate for nMOS) does not reduce leakage, or even increases it. It is especially important for DRAM data retention and for designs that bias the gate negative to cut standby leakage.
Punch-through
The extreme state of short-channel effects, where current flows with no gate control at all. Treat it as the limit that sets the minimum gate length and the maximum drain voltage of a transistor.

FAQ

What is the difference between DIBL and punch-through?

In both, the drain voltage lowers the barrier on the source side. In DIBL, the barrier near the channel surface drops and the threshold voltage falls, but the gate still controls the current. In punch-through, the source and drain depletion regions merge deep in the substrate and current flows along a path the gate cannot reach, so the transistor cannot be turned off. It helps to think of punch-through as DIBL taken to the extreme.

How can I tell DIBL from GIDL in an Id-Vg curve?

DIBL appears as a leftward shift of the subthreshold curve when the drain voltage is raised, and the current still falls as the gate voltage is lowered. GIDL appears as current that starts rising again when the gate voltage is pushed well below threshold. In short, DIBL shows up as a threshold-voltage shift, and GIDL as an upturn in current on the low gate-voltage side.

Why do halo (pocket) implants suppress short-channel effects?

Locally raising the doping near the source and drain edges with dopants of the same type as the channel keeps the drain depletion region from spreading into the channel. That suppresses DIBL, threshold-voltage roll-off and punch-through, with less mobility loss than raising the doping of the whole channel. Because doping near the junction goes up, junction leakage and junction capacitance can increase.

Do these effects disappear in FinFETs and GAA transistors?

They do not disappear, but DIBL and punch-through are greatly reduced. The gate surrounds a thin channel from several sides, so the drain field has less influence and there are fewer deep current paths out of the gate's reach. Bulk FinFETs, whose fins connect to the substrate, usually get a heavily doped punch-through stopper implanted at the base of the fin. GIDL is set by the field at the drain edge, so it still has to be managed through junction design and bias conditions even with new structures.

Check your understanding

Which correctly describes DIBL (drain-induced barrier lowering)?

  1. AThe gate insulator breaks down over time
  2. BMetal atoms in wiring migrate due to current
  3. CThe higher the drain voltage, the lower the potential barrier at the source, lowering the threshold voltage
Show answer and explanation

Answer: C. The higher the drain voltage, the lower the potential barrier at the source, lowering the threshold voltage

With a short gate, the drain's field reaches toward the source and lowers the source-channel potential barrier. Threshold voltage therefore falls as drain voltage rises, increasing off-state leakage. DIBL is quoted as threshold shift per volt of drain bias (mV/V), kept to a few tens of mV/V or less in advanced transistors. In amplifiers it also lowers output resistance.

Which phenomenon increases off-state leakage because band-to-band tunneling current flows due to the strong field where the gate overlaps the drain?

  1. ADIBL
  2. BNBTI
  3. CGIDL (gate-induced drain leakage)
Show answer and explanation

Answer: C. GIDL (gate-induced drain leakage)

Even when a transistor is off, a large gate-to-drain voltage bends the bands sharply near the drain edge of the gate, and band-to-band tunneling causes current to flow—GIDL, which in an nMOS notably grows as the gate is driven more negative. It is a problem in devices requiring ultra-low leakage such as DRAM cell transistors and is controlled by engineering the drain-edge doping and field. DIBL is threshold lowering by drain voltage, and NBTI is a pMOS degradation mechanism.

Which correctly describes punch-through in a MOSFET?

  1. AA drop in channel mobility with temperature
  2. BThe source and drain depletion layers merge and current flows that the gate cannot control
  3. CDielectric breakdown of the gate insulator
Show answer and explanation

Answer: B. The source and drain depletion layers merge and current flows that the gate cannot control

With a short channel and light substrate doping, the drain's depletion region can merge with the source's under drain bias, so current flows deep in the substrate independent of the gate and the device cannot turn off—punch-through. Remedies include heavily doped halo (pocket) implants beneath the source/drain, shallower junctions, and, as in FinFETs and GAA devices, wrapping the gate around the channel to eliminate uncontrolled paths.

  1. What is the main purpose of halo (pocket) implants, which implant dopants of the same type as the channel at an angle near the source/drain edges?
  2. Which describes a short-channel effect in MOSFETs?
  3. Which combination lists the main components of leakage current in a MOSFET in the off state?

Practice MOSFET questions

Key terms explained

DIBL
Short for drain-induced barrier lowering. In short-channel MOSFETs, a higher drain voltage lowers the potential barrier at the source, reducing the threshold voltage and increasing off-state leakage.
GIDL (gate-induced drain leakage)
Off-state leakage caused by band-to-band tunneling in the strong field where the gate overlaps the drain. It is a concern for data retention in DRAM, among others.
Punch-through
A condition in which the source and drain depletion regions merge and current flows that the gate cannot control. It occurs when the channel is too short or the substrate doping is too low.
Short-channel effect
Phenomena in which, as gate length shrinks, the drain's electric field lowers the threshold voltage and increases off-state leakage current.
Halo implant (pocket implant)
Angled implantation of dopant of the same type as the channel near the source and drain edges. It limits the spread of the drain depletion region and suppresses short-channel effects.
LDD structure
Short for lightly doped drain. The drain is made lightly doped only at its edge next to the gate, relaxing the electric field and suppressing hot-carrier degradation.
Threshold voltage
The gate voltage at which a channel (inversion layer) forms in a MOSFET and current starts to flow. Written as Vth.
FinFET
A 3D transistor whose channel stands up like a fin and is surrounded by the gate on three sides. It suppresses short-channel effects well.

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