Automotive Semiconductors and Functional Safety

Which is the most appropriate example of a latent fault in ISO 26262?

  1. AA fault that, occurring alone, cannot be detected or controlled even by safety mechanisms and immediately leads to violation of a safety goal
  2. BA state in which the ECC correction circuit is broken, but nothing happens as long as no memory error occurs, so it remains unnoticed
  3. CA fault that was detected by a safety mechanism and reported to the driver with a warning lamp
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Answer: B. A state in which the ECC correction circuit is broken, but nothing happens as long as no memory error occurs, so it remains unnoticed

A latent fault is a fault that is not hazardous by itself and remains unnoticed by both safety mechanisms and the driver. For example, even if the correction circuit of the ECC, a safety mechanism, is broken, it does not show up as long as there are no memory errors. If a bit error then occurs in memory, it is not corrected and can lead to a hazard. Because a hazard arises only when two faults coincide, the latent fault metric (LFM) evaluates how small the proportion of latent faults is. A fault that immediately becomes hazardous is a single-point fault, and a detected fault is not a latent fault.

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More Automotive Semiconductors and Functional Safety questions

  1. The total failure rate of safety-related hardware is 1000 FIT, of which single-point faults and residual faults (faults that remain undetected by safety mechanisms) total 5 FIT. What is the single-point fault metric (SPFM)?
  2. A safety mechanism with 99% diagnostic coverage is added to a circuit with a failure rate of 200 FIT. What is the failure rate of the faults that remain undetected by the safety mechanism?
  3. Which correctly describes the fault tolerant time interval (FTTI) in ISO 26262?
  4. Which correctly describes how a lockstep CPU, used as a safety mechanism in automotive microcontrollers, works?
  5. What is the main reason for offsetting the execution of the two cores in a lockstep CPU by a few clock cycles, or placing the two cores apart on the chip?