Logic circuits

In a synchronous circuit, what determines the maximum clock frequency at which it can operate?

  1. AThe delay of the fastest path
  2. BOnly the supply voltage
  3. CThe delay of the slowest path between flip-flops (the critical path)
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Answer: C. The delay of the slowest path between flip-flops (the critical path)

The clock period must be longer than the time it takes data leaving one flip-flop to pass through the logic and reach the next flip-flop while meeting its setup time. The path with the largest delay (the critical path) therefore sets the maximum clock frequency.

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  3. When is the output of a 2-input OR gate 0?
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