CPUs and architecture

What is the typical size of a cache line (cache block) in many current CPUs?

  1. A1 byte
  2. B64 bytes
  3. C64 MB
Show answer and explanation

Answer: B. 64 bytes

Many CPUs transfer data between cache and main memory in lines of about 64 bytes. Because data at nearby addresses is often used soon after (spatial locality), fetching it together is efficient.

  • A. Transferring one byte at a time would be inefficient.
  • B. Correct. 64 bytes is typical.
  • C. 64 MB is on the order of an entire cache's capacity, not a line size.
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More CPUs and architecture questions

  1. In a pipeline, when the next instruction immediately uses the result of the previous one (a data hazard), which technique passes the result directly to the next instruction without waiting for it to be written to the register?
  2. Which correctly describes little-endian byte order?
  3. Which technique lets one CPU core process instructions from multiple threads at the same time to make better use of the core's execution units?
  4. In microcontrollers and similar devices, which scheme assigns peripheral registers to the same address space as memory and operates them with ordinary memory read/write instructions?
  5. What is the role of the watchdog timer built into microcontrollers?