Memory Hierarchy

With 64 TLB entries and a 4 KB page size, how much memory can be accessed without TLB misses (the TLB reach)?

  1. A64 KB
  2. B256 KB
  3. C4 MB
Show answer and explanation

Answer: B. 256 KB

Each TLB entry holds the translation for one page, so TLB reach = entries × page size = 64 × 4 KB = 256 KB. Programs that frequently touch a wider range suffer more TLB misses. With 2 MB huge pages, the same 64 entries reach 64 × 2 MB = 128 MB. 64 KB results from mistaking the page size for 1 KB, and 4 MB from a miscalculation.

  • A. 64 KB results from assuming a 1 KB page.
  • B. Correct. 64 entries × 4 KB = 256 KB.
  • C. 4 MB is a miscalculation.
Practice this topic Back to topic

More Memory Hierarchy questions

  1. Which pair correctly states the main advantage and drawback of using large pages (huge pages)?
  2. When each row of a 2D array is 4,096 bytes (a power of two), walking down a column can cause many misses even though the cache has spare capacity. Which countermeasure is effective?
  3. Roughly how many times longer is a main-memory DRAM access than an L1 cache hit (for typical PC or server CPUs)?
  4. What is the role of the valid bit attached to each cache line?
  5. What is the main effect of a victim cache, a small fully associative buffer that temporarily holds lines evicted from the L1 cache?