Dopant Diffusion in Silicon: Fick's Law and √(Dt) Explained

In everyday life

Put one drop of colored water on a block of firm agar gel, and leave it alone. Over several days, the color slowly bleeds outward. Nobody stirs it; the color particles spread out on their own. This spreading, caused by the random motion of particles, is called diffusion.

In water, currents (convection) would mix things much faster. In a gel, you see diffusion alone.

The same thing happens inside a chip. To set its electrical behavior, silicon gets tiny amounts of impurities such as boron or phosphorus. Each time the wafer goes through a hot step at around 1,000 °C, these impurities spread a little further.

Transistors are built by placing n-type and p-type regions side by side, at the scale of nanometers (nm, a billionth of a meter). If impurities spread too far, the boundaries shift and the transistor does not work as designed. So fabs estimate how far impurities will spread, and choose temperatures and times to match.

The technology side: adding impurities, and the role of heat

Adding impurities to silicon is called doping. The method that spread in the 1950s used diffusion itself. Silicon was heated to a high temperature in a gas containing the impurity, and the impurity soaked in from the surface. This method is called thermal diffusion.

Thermal diffusion was developed in the early 1950s at Bell Labs in the US. Temperature and time set how deep the impurity went. By 1954 it was used for transistors, and for silicon solar cells with diffused boron.

Later, most of these steps switched to ion implantation. Here, impurity atoms are sped up by electric force and fired into the silicon like bullets. The amount can be counted from the current, and the depth is set by how hard the atoms are accelerated. That makes it far more precise than thermal diffusion. The switch took place from the 1970s on.

But firing atoms in is not enough on its own. Most implanted atoms do not sit at proper sites in the crystal, so they cannot supply the particles that carry current. The crystal is damaged, too.

So the wafer is heated once more to repair the damage and settle the impurities into crystal sites. This heat treatment is called annealing. Getting the impurities to the point where they can supply current carriers is called "activation."

The trouble is that impurities also diffuse at annealing temperatures. More hot steps follow, such as depositing films and oxidizing. So even after the doping method changed, diffusion remained as an "unavoidable side effect." Thermal diffusion itself is still used in steps that form deep regions, and in solar cells (thermal diffusion vs. ion implantation).

How it works 1: random motion creates a flow

In hot silicon, an impurity atom now and then jumps to a neighboring site in the crystal. Which way it jumps is pure chance: right and left are equally likely. The atom is not "trying" to reach the less crowded side.

Even so, a flow from high to low concentration appears as a whole. Picture two neighboring boxes. The left box holds 8 atoms and the right box holds 2. Each atom has a 50% chance of jumping into the other box.

On average, 4 atoms jump from left to right, and 1 jumps from right to left. The net result is 3 atoms moving from left to right. Each atom moves at random. But more atoms leave the side that holds more of them. So the net flow points from high concentration to low.

This net flow gets larger as the concentration changes more steeply. The rule "the flow is proportional to the slope of the concentration" is called Fick's first law. Fick, a German-born physiologist, published it in 1855.

The constant in this proportion is called the diffusion coefficient (D). It measures how easily atoms jump: the bigger it is, the faster they spread. Its unit is cm²/s (an area divided by seconds), for a reason the next section makes clear.

Once the concentration is the same everywhere, jumps to the left and right balance out, and the net flow drops to zero. Even then, each atom keeps jumping. Only the net flow has stopped.

How it works 2: the spreading distance is √(Dt)

So how far do impurities spread? Follow a single atom. It jumps right and left at random, so it keeps going out and coming back. As a result, it ends up not far from where it started, considering how many jumps it made.

Probability math shows that the typical distance from the start grows with the square root of the number of jumps. A square root is the number that, multiplied by itself, gives the original number. It is written √ (√100 = 10). After 100 jumps, an atom is typically only about 10 jumps' worth away. The number of jumps grows in proportion to time. So the spreading distance grows with the square root of time.

As a formula, the typical spreading distance is √(D × t), where t is time. D has the unit cm²/s, so multiplying by seconds gives cm². Taking the square root then gives cm, which is a length.

Because of how square roots work, doubling the time multiplies the distance by only √2, about 1.4. It takes 4 times the time to double the distance, and 100 times the time to go 10 times as far. Impurities spread a lot at first, and after that the spreading slows down.

This article uses √(Dt), with no extra factor, as the "spreading scale," and every number here is calculated with it. Real profiles trail off gradually, so the factor depends on where you decide the spreading "ends." Textbooks often use 2√(Dt) instead.

By the numbers: one hour at 1,000 °C

In silicon at 1,000 °C, the diffusion coefficient is about 1.5×10⁻¹⁴ cm²/s for boron and about 1.3×10⁻¹⁴ cm²/s for phosphorus. These are calculated from values often used in textbooks. Different measurements disagree by a few tens of percent.

Let's work out boron heated at 1,000 °C for one hour (3,600 seconds).

1. D × t = 1.5×10⁻¹⁴ × 3,600 ≈ 5.4×10⁻¹¹ cm²
2. Taking the square root gives about 7.4×10⁻⁶ cm
3. In nanometers, that is about 74 nm

74 nm is about a thousandth of the width of a human hair (about 0.08 mm). Yet for an advanced transistor, it is a long way. In the "2 nm" test chip IBM announced in 2021, the gate was 12 nm long. Just one hour in a furnace spreads impurities several times that distance.

How it works 3: temperature changes D by orders of magnitude

To jump to a neighboring site, an atom needs a crystal defect nearby. A defect is a hole where an atom is missing, or an extra atom squeezed into a gap. It also has to get over an energy "hill." Both the number of defects and the share of atoms that can climb the hill rise sharply with temperature. So the diffusion coefficient changes exponentially with temperature. In other words, it changes by orders of magnitude.

The Arrhenius equation describes this relationship ("Arrhenius Equation in Chips"). The height of the hill is called the activation energy. It is about 3.5 eV for boron and about 3.7 eV for phosphorus (eV is a unit of energy).

With a hill this high, going from 1,000 °C to 1,100 °C makes the diffusion coefficient about 10 times larger. From 900 °C to 1,000 °C, it grows 15–17 times. For the same time, the spreading distance grows by √10, about 3 times. So a 100 °C difference in temperature works like a tenfold difference in time.

At room temperature, by contrast, boron and phosphorus do not move at all in practice. Applying the equation directly at 25 °C gives a boron diffusion coefficient of around 10⁻⁵⁹ cm²/s. Even after 10 years, almost no atom would make a single jump. So there is no need to worry that impurities will spread and break a chip during use.

How it works 4: two shapes of impurity profile

For doping by thermal diffusion, textbooks look at two typical cases. In both, the width of the profile (how the concentration changes with depth) is measured with √(Dt) as the yardstick.

The first case keeps the surface concentration constant while heating. Impurities are always resupplied at the surface, so the amount inside keeps rising over time. The profile is highest at the surface and falls off smoothly with depth. This shape is named after a math function: the complementary error function (erfc).

The second case puts in a fixed amount first, then heats with no resupply. The total stays the same, so over time the peak gets lower and wider. Its shape is half of a "bell curve" (a Gaussian distribution).

Older thermal diffusion used these two cases in order. First, the surface was held at a constant concentration during a short heat, putting a set amount in at a shallow depth. This first step is called predeposition.

Next, the supply was stopped and the wafer was heated again to push the impurities deeper. This step is called drive-in. The advantage is that the amount and the depth can be set separately.

Junction depth

Suppose you add boron to n-type silicon to make a p-type layer. Where boron outnumbers the phosphorus already there, the silicon becomes p-type. Where it does not, the silicon stays n-type. The point where the two concentrations are equal is the boundary between p-type and n-type (a PN junction). The distance from the surface to that point is called the junction depth.

The more heat, the deeper the profile reaches, and the deeper the junction gets. With a constant surface concentration, the junction depth grows in proportion to √(Dt). With a fixed amount, it deepens a little more slowly, because the peak drops as it spreads.

Where it matters: thermal budget and short anneals

Diffusion adds up over every hot step. If each step's diffusion coefficient is treated as constant, the total spreading is set by adding up "diffusion coefficient × time" for every step. The total heat a wafer receives is called its thermal budget.

The diffusion coefficient is very sensitive to temperature, so the hottest steps make up most of the total. One minute at 1,100 °C equals about 10 minutes at 1,000 °C. The key is to keep the time at high temperature as short as possible.

This is where annealing poses a dilemma. Activation and damage repair need a high temperature. But a long time at high temperature lets impurities spread. The answer was to make the time at high temperature extremely short.

In the past, many wafers went into a furnace together and were heated for tens of minutes. Rapid thermal processing (RTP) instead heats one wafer at a time with lamp light, in a few seconds (furnace anneal vs. RTA vs. laser anneal).

A spike anneal goes further. It starts cooling the wafer as soon as it reaches the peak temperature, so the wafer stays near the peak for only about 1 second. Beyond that are flash lamp annealing and laser annealing, which hit the wafer with intense light for an instant. They heat the surface for about 1 millisecond, or even less with some methods.

The table keeps the temperature the same and compares only the time. Real short anneals go to higher temperatures for better activation. Even so, the time at high temperature is so short that the spreading stays far smaller than in a furnace.

In practice, though, the crystal damage from implantation makes diffusion temporarily faster early in the anneal (transient enhanced diffusion (TED)). The calculations in this article leave out effects like this and show only the basic form.

Where the same idea shows up

How heat spreads

Heat also spreads, from hot areas to cooler ones, following an equation of the same form as diffusion. Temperature takes the place of concentration, and "thermal diffusivity" takes the place of the diffusion coefficient. Silicon's thermal diffusivity is about 0.8 cm²/s at room temperature. That is about 50 trillion times the diffusion coefficient of boron at 1,000 °C.

Using √(Dt), heat spreads about 0.3 mm in 1 millisecond, and even less at high temperature. That is why a millisecond anneal heats only the front side of a wafer about 0.78 mm thick (junction temperature calculator).

Electrons and holes in a PN junction

At the boundary between p-type and n-type, electrons diffuse from the n-type side into the p-type side. Holes (gaps left where an electron is missing) diffuse the other way, from p-type to n-type. Together they make a diffusion current. This leaves a layer at the boundary with no carriers free to move. The electric force that forms there holds back any further diffusion (diagram of the PN junction depletion layer).

In silicon at room temperature, the electron diffusion coefficient is at most about 36 cm²/s. At that rate, electrons spread about 2 µm in 1 nanosecond. Take t as the average time before an electron disappears; then √(Dt) is called the diffusion length. This length affects how sensitive solar cells and camera sensors are.

Delay in long wires

A long wire on a chip can be treated as resistance and charge-storing parts (capacitance) spread finely along its whole length. In such a wire, the way a voltage travels follows an equation of the same form as diffusion.

Distance grows with the square root of time. Turned around, the time needed grows with the square of the distance. So the delay set by the wire's own resistance and capacitance becomes about 4 times longer when the wire is twice as long. Real chips insert relay circuits (repeaters) along long wires to hold down this growth (interconnect RC delay calculator).

Common misconceptions

Learn more

• Terms: thermal diffusion / drive-in / ion implantation / annealing / transient enhanced diffusion (TED) / oxidation-enhanced diffusion (OED)
• Try the numbers: thermal oxide thickness (a thick oxide grows roughly with the square root of time, because oxygen has to diffuse through the film to reach the silicon) / resistivity and doping concentration
• Related explainers: "Arrhenius Equation in Chips" / "How Are Chips Made?"