English
Menu

In-Order vs Out-of-Order Execution: Key Differences Explained

An in-order CPU issues and executes instructions in program order. When an earlier instruction waits, for example on a cache miss, the instructions behind it stop too. An out-of-order CPU checks dependencies, executes whichever instructions are ready first, and commits the results in program order through a reorder buffer (ROB). Because it can make progress on other instructions during waits, it achieves higher IPC, but it needs register renaming and instruction-selection logic, which increase circuit size and power.

AspectIn-order executionOut-of-order execution
Order of issue and executionProgram orderReady instructions are executed first, out of order
Committing results (retirement)Program orderIn program order, through the reorder buffer (ROB)
When an earlier instruction is waitingLater instructions stop too (stall)Independent later instructions proceed first
Handling data hazardsForwarding and stalls. Instruction ordering is left to the compilerForwarding plus dynamic instruction scheduling in hardware
False dependencies (WAR, WAW)Since order is preserved, they rarely cause problemsRemoved by register renaming, which reassigns physical registers
Main additional circuitryLittle. A simple pipelineRename tables, physical registers, issue queues, the ROB, load/store queues
Impact of cache missesLarge. The pipeline tends to stall on every missOther instructions proceed within a window of hundreds of instructions, hiding part of the wait
IPCLower. Below out-of-order at the same issue widthHigh. Combined with a wide issue width, well above 1
Circuit size and powerSmall. Performance per area and per watt is easy to raiseLarge. Instruction-selection logic and the ROB add area and power
Where it is usedMicrocontrollers, small embedded cores, some cores that prioritize power saving, GPU compute coresHigh-performance cores in PCs, servers and smartphones

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

In-order execution
When you want to keep area and power small, or make execution time easy to predict. Used in microcontrollers, embedded cores, and designs that line up many small cores.
Out-of-order execution
When you want to run a single thread as fast as possible. Used in the high-performance cores of PCs, servers and smartphones.
Combined
Some chips combine out-of-order high-performance cores with power-saving cores that are in-order or reduced-size out-of-order. Heavy work goes to the high-performance cores and light work to the power-saving cores, balancing performance and power.

FAQ

Can out-of-order execution change a program's results?

Not within a single thread. Even when the execution order is changed, true data dependencies (RAW) are respected, and results are committed in program order through the reorder buffer. When a branch misprediction or exception occurs, the results of later instructions are discarded and the correct state is restored, so from the outside it looks as if the program ran in order.

Can an in-order CPU execute multiple instructions per cycle?

Yes. In-order superscalar processors issue adjacent independent instructions at the same time while preserving order. However, if an earlier instruction stalls, later ones cannot proceed, so IPC does not rise as much as with out-of-order execution.

What do register renaming and the ROB each do?

Register renaming removes the false dependencies (WAR and WAW) caused by reusing the same register names, by reassigning physical registers, which increases the number of instructions that can run in parallel. The ROB holds the results of instructions executed out of order and commits them in program order, enabling precise exceptions.

How can the performance of an in-order CPU be improved?

The compiler arranges instructions in an order that avoids waits, for example by placing instructions that use a load's result farther from the load. Besides reducing stalls with forwarding, data layouts that reduce cache misses and prefetching are also effective.

Check your understanding

Which technique examines instruction dependencies and executes ready instructions in an order different from the program order to improve performance?

  1. AIn-order execution
  2. BOut-of-order execution
  3. CSingle-cycle execution
Show answer and explanation

Answer: B. Out-of-order execution

Out-of-order execution sets aside instructions waiting on earlier results or memory data and executes later, ready instructions first—especially valuable for doing useful work during cache-miss stalls. It requires logic to find ready instructions in a window of hundreds, register renaming and a reorder buffer to commit results in order, increasing circuit size and power.

In an out-of-order CPU, which mechanism commits (retires) the results of instructions executed out of order in the program's original order?

  1. AReorder buffer
  2. BSnoop filter
  3. CTLB
Show answer and explanation

Answer: A. Reorder buffer

The reorder buffer holds results of instructions executed out of order and commits (retires) them in program order; in modern high-performance cores it spans hundreds of instructions. On a branch misprediction or exception, results of later instructions are discarded to restore the correct state, so execution appears to follow program order from the outside (precise exceptions).

What is the main purpose of register renaming in out-of-order CPUs?

  1. ATo reduce the number of registers and make the circuit smaller
  2. BTo reassign physical registers without changing the register names used by the program, removing false dependences (WAR and WAW)
  3. CTo encrypt register values
Show answer and explanation

Answer: B. To reassign physical registers without changing the register names used by the program, removing false dependences (WAR and WAW)

ISAs have only about 16–32 architectural registers, so names are reused and create false dependences unrelated to actual data flow—write-after-read (WAR) and write-after-write (WAW). Register renaming dynamically maps them onto hundreds of physical registers, assigning a fresh one on each write to remove these false dependences and expose more parallelism. True dependences (read-after-write, RAW) cannot be removed.

  1. What is the processor design called that issues and executes multiple instructions simultaneously in one clock cycle?
  2. In a pipeline, when the next instruction immediately uses the result of the previous one (a data hazard), which technique passes the result directly to the next instruction without waiting for it to be written to the register?
  3. Which metric indicates the number of instructions executed per clock?

Practice CPUs and architecture questions

Key terms explained

Out-of-order execution
Executing instructions as soon as their dependencies allow, in a different order from the program, to improve performance. Results are committed in program order through a reorder buffer.
Superscalar
A processor design that issues and executes several instructions per clock cycle. It has multiple execution units and processes independent instructions in parallel.
IPC
Short for instructions per cycle: the number of instructions executed per clock. It expresses design efficiency; performance is roughly IPC times clock frequency. Its reciprocal is CPI.
Pipelining
A method that splits instruction processing into stages such as fetch, decode and execute, and processes several instructions at once, each offset by a stage.
Branch prediction
A technique that predicts the outcome of conditional branches before they execute, so later instructions can proceed without stalling the pipeline. A misprediction forces the work to be redone.

Related comparisons