Reliability

Which correctly describes latch-up in CMOS circuits?

  1. ANormal operation for holding data
  2. BA phenomenon in which a parasitic thyristor structure turns on and a large current keeps flowing between power and ground
  3. CA phenomenon in which the clock stops
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Answer: B. A phenomenon in which a parasitic thyristor structure turns on and a large current keeps flowing between power and ground

CMOS structures contain a parasitic PNPN thyristor formed by the wells and substrate of the pMOS and nMOS. If noise or the like turns it on, a large current keeps flowing between power and ground, and in the worst case the device is destroyed. Countermeasures include strengthening well contacts and using SOI.

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More Reliability questions

  1. Which phenomenon degrades transistor characteristics when carriers accelerated by the high electric field near the drain are injected into the gate dielectric?
  2. Which failures are mainly evaluated by temperature-humidity-bias tests (THB and HAST)?
  3. Which distribution, often used in reliability data analysis, can represent early-failure, random-failure and wear-out types depending on its shape parameter?
  4. Which phenomenon creates voids as metal atoms move due to internal stress in wiring, even without current flowing?
  5. What is the phenomenon called in which needle-like metal crystals grow from the surface of tin plating and short to an adjacent terminal?