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PLL vs DLL: Key Differences Explained

Both detect the phase error relative to a reference clock and use feedback to drive it to zero, but they adjust different things. A PLL adjusts the frequency of a voltage-controlled oscillator (VCO) and aligns the clock it generates itself with the reference, so combined with a divider it can produce frequencies many times the reference. A DLL passes the input clock itself through a delay line and only adjusts that delay to align the phase, so it cannot change the frequency, but jitter does not accumulate and the loop is stable and easy to design.

AspectPLLDLL
NamePhase-Locked LoopDelay-Locked Loop
What it controlsVCO frequency (phase is the integral of frequency)The delay of the delay line
Main building blocksPhase-frequency detector, charge pump, loop filter, VCO, feedback dividerPhase detector, charge pump, loop filter (capacitor), voltage-controlled delay line
Output clockA clock generated by the VCO itselfA delayed version of the input clock
Frequency multiplicationPossible. A 1/N divider in the feedback gives N times the reference (fractional schemes also exist)Basically not possible. The output has the same frequency as the input (some schemes multiply by combining multiphase outputs)
JitterVCO fluctuations accumulate cycle by cycle, and only components below the loop bandwidth are corrected. Reference jitter components above the bandwidth are removedThe delay line does not accumulate jitter. Input jitter passes almost unchanged to the output
Loop stabilityThe VCO acts as an integrator, making the loop second order or higher, so the loop filter must be designed with phase margin in mindThe delay line has no integrating action, so the loop can be first order, stable and easy to design
LockingCan lock over a wide frequency range, but takes longer to lockLocks quickly, but the delay range is limited and false lock (locking one cycle off) must be watched for
Typical usesGenerating high-frequency clocks from a crystal reference, RF frequency synthesizers, SerDes clocks and clock and data recovery (CDR)Aligning DDR DRAM output timing with the clock, clock deskew, multiphase clock generation

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

PLL
When you need a clock at a different frequency from the reference (usually many times higher). Generating CPU or SerDes clocks from a crystal reference, or generating radio frequencies.
DLL
When the same frequency is fine and you want to cancel on-chip delay to align clock phase. Aligning DDR DRAM data output timing, and clock deskew.
Combined
A common combination is to generate a clock at the required frequency with a PLL and then, in memory interfaces and similar circuits, use a DLL referenced to that clock for fine phase adjustment (for example, shifting a strobe by 1/4 cycle).

FAQ

Why can't a DLL change the frequency?

Because a DLL's output is the input clock delayed by a delay line. No matter how the delay is changed, the edge spacing stays the same as the input, so the frequency does not change. A PLL has a VCO that oscillates on its own and aligns its divided clock with the reference, so it can produce N times the reference frequency.

Why does jitter not accumulate in a DLL?

Because each output edge of a DLL is a delayed copy of an input edge and does not inherit errors from the previous cycle. In a PLL's VCO, each cycle starts where the previous one ended, so fluctuations add up and remain until the loop corrects them. On the other hand, a DLL passes input jitter straight through.

How is the PLL loop bandwidth chosen?

A wider bandwidth corrects VCO fluctuations quickly but lets more reference clock jitter through. A narrower bandwidth rejects reference jitter well, but leaves more VCO fluctuation and slows locking. It is chosen by considering whether the reference or the VCO has lower noise, along with loop stability (phase margin).

Why are DLLs used in DDR DRAM?

The on-chip clock path and output circuits have delays that vary with voltage and temperature. Canceling this delay with a DLL lets data be output aligned with the edges of the external clock. There is no need to change the frequency, so a DLL, which adds little jitter, is well suited.

Check your understanding

Which circuit generates a clock at a frequency such as an integer multiple of a reference clock while locking its phase to the reference?

  1. APLL (phase-locked loop)
  2. BRectifier
  3. CSample-and-hold circuit
Show answer and explanation

Answer: A. PLL (phase-locked loop)

A PLL consists of a phase detector, loop filter, voltage-controlled oscillator (VCO) and divider, steering the VCO so that its divided output stays in phase with the reference clock. A divide ratio of N yields N times the reference frequency, so a 25 MHz crystal can produce a multi-GHz CPU clock. Fractional-N division synthesizes fine frequency steps, and PLLs also serve as radio local oscillators and for clock recovery in high-speed serial links.

Which correctly describes clock skew in a synchronous circuit?

  1. AVariation of the clock frequency over time
  2. BThe difference in the time the clock signal arrives at different flip-flops
  3. CThe clock signal voltage exceeding the supply voltage
Show answer and explanation

Answer: B. The difference in the time the clock signal arrives at different flip-flops

Clock skew is the difference in arrival times of the same clock at different flip-flops, caused by differences in wire length and load. A late capture clock helps setup but hurts hold, and vice versa. Clock tree synthesis (CTS) builds the chip-wide clock tree, balancing buffer placement and wire lengths to keep skew within tens of picoseconds. Variation of the period over time is jitter.

What is the main purpose of clock tree synthesis (CTS) in the place-and-route stage?

  1. ATo reduce variation (skew) in the time the clock signal reaches each flip-flop
  2. BTo raise the supply voltage
  3. CTo fix design rule violations in the layout
Show answer and explanation

Answer: A. To reduce variation (skew) in the time the clock signal reaches each flip-flop

If the clock reaches millions of flip-flops at varying times, timing violations result. CTS distributes the clock through a tree of buffers to minimize variation in arrival times (skew). Because the clock toggles constantly, the clock tree can consume a large share of chip power. Raising supply voltage or fixing DRC violations are unrelated goals.

  1. Why does timing fluctuation (jitter) of the sampling clock become a problem when converting high-frequency signals?
  2. Why are crystal oscillators widely used as clock sources for watches and microcontrollers?

Practice Analog and electronic circuits questions

Key terms explained

PLL (phase-locked loop)
A circuit that detects the phase difference from a reference clock and controls an oscillator to produce a clock locked to the reference, for example at an integer multiple of its frequency. It is used to generate CPU clocks and synthesize radio frequencies.
Jitter
Small fluctuations in the timing of clock or signal edges from their ideal positions. When sampling high-frequency signals, even slight jitter causes large voltage errors.
Clock skew
The difference in arrival time of the same clock signal at different flip-flops. Because it changes setup and hold margins, clock tree synthesis keeps it small.
Phase margin
How far the phase lag is from 180° at the frequency where the feedback loop gain is 1 (0 dB). A small margin causes ringing, and zero or negative margin causes oscillation; 45-60° or more is a common target.

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