English
Menu

Jitter vs Phase Noise: Key Differences Explained

Jitter and phase noise are two views of the same fluctuation in a clock or oscillator. Jitter is in the time domain: it expresses, in seconds (ps or fs), how far each edge deviates from its ideal time. Phase noise is in the frequency domain: it expresses the noise level at a given frequency offset from the carrier, as a ratio to the carrier in dBc/Hz. Integrating phase noise over a frequency range converts it to RMS jitter, but the result depends on the integration range, so the range must always be stated.

AspectJitterPhase noise
DomainTime domainFrequency domain
Quantity expressedDeviation of edge times from their ideal timesRatio of noise power per 1 Hz to carrier power at each offset frequency from the carrier (single sideband)
UnitsSeconds (ps, fs), or UI (fraction of one bit period)dBc/Hz (given together with the offset frequency)
Typical metricsPeriod jitter, cycle-to-cycle jitter, TIE (time interval error). RMS and peak-to-peak valuesValues or curves at each offset, e.g. −140 dBc/Hz at 1 MHz offset
Main instrumentsOscilloscopes, time interval analyzers, bit error rate testersPhase noise analyzers, spectrum analyzers with phase noise measurement capability
Random vs deterministic componentsRandom jitter is handled as an RMS value and deterministic jitter as a peak-to-peak value, and total jitter is derived from the target error rateRandom components appear as a smooth curve, and periodic components as lines at specific frequencies (spurs)
Conversion between themA jitter value alone does not reveal the frequency profile of the phase noiseIntegrating over offsets f1–f2 converts it: RMS jitter = √(2∫10^(L(f)/10) df) ÷ (2π f0)
Effect of rangeThe value changes with the instrument bandwidth and how many cycles are observedThe converted RMS jitter changes with the integration range (e.g. 12 kHz–20 MHz)
What it tells youA quantity that directly affects timing margin (setup, horizontal eye opening)Which frequencies have large fluctuations. Clues to the PLL loop bandwidth and the sources of noise
Main fields of useTiming analysis of digital circuits, high-speed serial linksRF oscillators, PLL and VCO design, clocks for high-speed ADCs

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Jitter
When you want to know the timing margin directly: clock uncertainty in static timing analysis, evaluating eye diagrams and error rates in high-speed serial links, etc.
Phase noise
When you want to know which frequencies the noise comes from: evaluating local oscillators in radios, designing PLL loop bandwidth, comparing oscillators, etc.
Combined
Clock source specifications often give both the phase noise curve and the RMS jitter converted over a fixed integration range. For high-speed ADC clocks, the SNR limit is set by −20 log₁₀(2π f tj), so it is estimated using the jitter derived from phase noise.

FAQ

How do you get RMS jitter from phase noise?

Convert the phase noise L(f) from dBc/Hz to a linear value, integrate it over the chosen offset range, and double it to get the mean-square phase fluctuation (rad²). Take the square root and divide by 2π f0 (f0 is the carrier frequency) to get the RMS jitter. For example, a 100 MHz clock with 1 mrad (RMS) of phase fluctuation has about 1.6 ps of jitter.

Why must the integration range be stated?

The total phase noise depends on the offset range over which it is integrated, and so does the converted RMS jitter. Without the range, values cannot be compared correctly with those of other oscillators. Clock specifications often use a fixed range such as 12 kHz–20 MHz.

Why do jitter values for the same clock differ between documents?

The definitions may differ (period jitter, cycle-to-cycle jitter, TIE), RMS and peak-to-peak values may be mixed, or the measurement bandwidth may differ. The peak-to-peak value of random jitter grows with longer observation time, so it is given together with an error rate.

Should I look at jitter or phase noise?

Jitter suits you if you want to know the timing margin in digital circuits or high-speed serial links; phase noise suits you if you want to know the noise sources or frequency-dependent behavior when designing RF oscillators or PLLs. They are two views of the same fluctuation, so use whichever fits the purpose.

Check your understanding

Why does timing fluctuation (jitter) of the sampling clock become a problem when converting high-frequency signals?

  1. ABecause the clock stops
  2. BBecause errors occur only for DC signals
  3. CBecause the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time
Show answer and explanation

Answer: C. Because the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time

If the sampling instant shifts by Δt, the signal's change during that time becomes error. Since a sine wave's slope is proportional to frequency, jitter limits SNR to −20 log₁₀(2πf·tj). Achieving 70 dB on a 100 MHz signal, for example, requires jitter below about 0.5 ps. In high-speed, high-resolution ADCs and radio receivers, a low-phase-noise clock source is therefore decisive.

In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?

  1. ABecause the hold check is performed only at falling clock edges
  2. BBecause jitter occurs only at high frequencies, and hold analysis is done at a lowered frequency
  3. CBecause hold compares against the same clock edge, so variation in the edge timing affects the launching and capturing sides equally and cancels out
Show answer and explanation

Answer: C. Because hold compares against the same clock edge, so variation in the edge timing affects the launching and capturing sides equally and cancels out

Period jitter is variation in the interval between one edge and the next. Setup is judged on the interval between the launching edge and the next edge, so with ±30 ps of jitter on a 1.0 ns period, the available time shrinks to 0.97 ns in the worst case. Hold compares launch and capture at the same edge, so whether that edge is early or late, both sides move together and the effect of jitter almost cancels out. However, the estimate of skew before the clock tree is built is included in the hold uncertainty as well.

Which statement about the eye diagram used to assess high-speed serial signal quality is correct?

  1. AIt overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is
  2. BThe more closed the eye, the better the signal
  3. CIt is a chart for checking the health of human eyes
Show answer and explanation

Answer: A. It overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is

An eye diagram slices the waveform at each bit period and overlays the pieces. An eye-shaped gap appears between the 0 and 1 traces; its height represents the margin against noise and its width the margin against timing variation (jitter). Channel loss, reflections and jitter close the eye. The receiver decides bits at the center of the eye, so its opening is a measure of quality.

  1. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  2. Which circuit generates a clock at a frequency such as an integer multiple of a reference clock while locking its phase to the reference?

Practice Analog and electronic circuits questions

Key terms explained

Jitter
Small fluctuations in the timing of clock or signal edges from their ideal positions. When sampling high-frequency signals, even slight jitter causes large voltage errors.
PLL (phase-locked loop)
A circuit that detects the phase difference from a reference clock and controls an oscillator to produce a clock locked to the reference, for example at an integer multiple of its frequency. It is used to generate CPU clocks and synthesize radio frequencies.
Eye diagram
A plot overlaying many bit periods of a waveform. The height of the central eye shows noise margin and its width shows timing margin.
Thermal noise (Johnson noise)
Noise caused by the thermal motion of electrons in a resistor. Its mean-square voltage is 4kTRΔf, proportional to temperature, resistance and bandwidth.
1/f noise (flicker noise)
Noise that grows larger at lower frequencies. In MOSFETs it comes from traps at the gate-oxide interface capturing and releasing carriers, and it matters in low-frequency analog circuits.

Related comparisons