Latch vs Flip-Flop: Differences Explained

Both store one bit, but they are triggered differently. A latch is level-sensitive: while its enable signal is active it is transparent and passes the input straight to the output, and when the enable goes inactive it holds the value. A flip-flop is edge-triggered: it captures the input only at the clock edge and ignores changes in between. A flip-flop is built from two latches working in opposite phases.

AspectLatchFlip-flop
TriggerLevel-sensitive: acts while the enable is activeEdge-triggered: acts only at the rising or falling clock edge
Output behaviorFollows the input while transparent, then holdsChanges only at the clock edge, stable otherwise
ConstructionA single storage stageTwo latches in series, working in opposite phases (master-slave)
Size and powerSmaller, with lower powerLarger, roughly twice the transistors
Timing analysisMore complex: time borrowing across the transparent phaseSimple: setup and hold times around the clock edge
Sensitivity to glitchesGlitches and races pass through while transparentImmune to input changes between clock edges
Typical usesCustom high-speed designs with time borrowing, clock-gating cellsRegisters, counters and state machines in synchronous design

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Latch
When area, power or speed justify the harder timing analysis, typically in custom or high-performance circuits.
Flip-flop
The default building block in synchronous design, because timing is simple and robust.
HDL tip
In Verilog or VHDL, an incomplete if or case statement in combinational logic creates an unintended latch. Assign a value in every branch to avoid it.

FAQ

What is the difference between a latch and a flip-flop in one sentence?

A latch is level-sensitive and transparent while its enable is active, while a flip-flop is edge-triggered and captures its input only at the clock edge.

Is a flip-flop made of latches?

Yes. A master-slave flip-flop is two latches in series, working in opposite phases.

Why do designers prefer flip-flops?

Timing analysis is simple, with setup and hold times around one clock edge, and glitches between edges do not matter.

How does an unintended latch appear in HDL code?

When a combinational always block or process does not assign an output in every branch (an incomplete if or case), synthesis keeps the old value and infers a latch.

Check your understanding

Which correctly describes the operation of a D latch?

  1. AIt captures the input only at the instant of the rising clock edge
  2. BIt always outputs the inverted input
  3. CWhile the enable signal is active, the input passes straight to the output; when it becomes inactive, the value is held
Show answer and explanation

Answer: C. While the enable signal is active, the input passes straight to the output; when it becomes inactive, the value is held

A D latch is level-sensitive: while enabled it is transparent, passing input straight to output, and when disabled it holds the value at that moment. It uses fewer transistors than a flip-flop and is sometimes used for speed via latch-based timing (time borrowing), but signals racing through during transparency make timing analysis harder. An edge-triggered D flip-flop is built from two latches clocked in opposite phases.

Which correctly describes the operation of a D flip-flop?

  1. AIt always passes input changes directly to the output
  2. BIt outputs the exclusive OR of two inputs
  3. CIt captures the value of the D input at a clock edge and holds it until the next edge
Show answer and explanation

Answer: C. It captures the value of the D input at a clock edge and holds it until the next edge

A D flip-flop captures its D input on the rising (or falling) clock edge and holds it until the next edge; changes between edges do not affect the output. It is the building block of sequential circuits—CPU registers, pipeline stage boundaries and counters—and is internally two latches in a master-slave arrangement. Correct capture requires meeting setup and hold times.

Which correctly describes the setup time of a flip-flop?

  1. AThe minimum time data must be held after the clock edge
  2. BThe minimum time the data input must be stable before the clock edge
  3. CThe time from power-on until it starts operating
Show answer and explanation

Answer: B. The minimum time the data input must be stable before the clock edge

For a flip-flop to capture correctly, data must be stable for a certain time before the clock edge—the setup time. A violation occurs if the data-path delay exceeds the clock period minus the setup time, and it can be fixed by slowing the clock. The time data must remain stable after the edge is the hold time. Violating either can capture wrong values or cause metastability.

  1. What is the state called when a flip-flop receiving an asynchronous signal violates setup or hold time and its output is temporarily neither 0 nor 1?
  2. What is an advantage of a synchronous circuit, in which all flip-flops operate on a common clock?
  3. Why does the code above create a latch, and what is the fix?

Practice Logic circuits questions

Key terms explained

Flip-flop
The basic element of sequential circuits that stores one bit. A D flip-flop captures its input at a clock edge.
Unintended latch
A latch created by synthesis when a description intended as combinational logic fails to assign an output under some condition, so the value must be held.

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