MOSFET

Which design makes the logic threshold of a CMOS inverter about half the supply voltage?

  1. ARemove the nMOS
  2. BSet the supply voltage to 0 V
  3. CMake the pMOS gate wider than the nMOS so that their drive strengths are balanced
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Answer: C. Make the pMOS gate wider than the nMOS so that their drive strengths are balanced

Hole mobility is lower than electron mobility, so a pMOS of the same size is weaker than an nMOS. Widening the pMOS gate to balance drive strength puts the logic threshold at about half the supply voltage and also equalizes rise and fall times.

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More MOSFET questions

  1. What is the advantage of a transmission gate, which connects an nMOS and a pMOS in parallel?
  2. What failure can occur when a voltage far above the rating is applied between the gate and source of a MOSFET?
  3. What is the main reason the channel mobility of a MOSFET is lower than the mobility inside bulk silicon?
  4. In a short-channel MOSFET, what is the main reason the drain current falls below the (VGS − Vth) square law and approaches a linear dependence?
  5. Which expression roughly represents the delay of a CMOS logic gate? (C: load capacitance, V: supply voltage, I: drive current)